Abstract: A planar TRAPATT diode includes a substrate selected from an area of a silicon wafer, a diffused region within the area, a mask of an insulating layer of SiO.sub.2, and a conductive layer of polycrystalline silicon. The silicon wafer includes a doped P region adjacent to the surface thereof and a heavily doped P.sup.+ region adjacent to the P region. The TRAPATT junction is a selected area below the surface at the interface between the diffused region, which is N.sup.+, and the P region. The polycrystalline silicon layer is the dopant source for the N.sup.+ diffused region and contacts the wafer in the selected area.