Patents by Inventor Fernand N. Forcier, Jr.

Fernand N. Forcier, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-layered, integrated circuit package having reduced parasitic noise characteristics
    Patent number: 5641988
    Abstract: A multi-layered, high performance integrated circuit package is disclosed having a number of design features which increase the performance and manufacturability of the integrated circuit package, and reduce the effects of parasitic noise generated within the package. The metallic layers connecting contact fingers formed on ledges around the periphery of a die cavity area, to their respective package pins are organized such that a ground metallic layer is interposed between each pair of input/output signal metallic layers, and each input/output signal metallic layer is sandwiched between a pair of metallic layers wherein one layer of the pair is connected to a voltage supply and the other layer of the pair is connected to a corresponding ground reference.
    Type: Grant
    Filed: October 30, 1995
    Date of Patent: June 24, 1997
    Assignee: VLSI Technology, Inc.
    Inventors: Chin-Ching Huang, Sang S. Lee, Ramachandra A. Rao, Fernand N. Forcier, Jr.
  • Multi-layered, integrated circuit package having reduced parasitic noise characteristics
    Patent number: 5625225
    Abstract: A multi-layered, high performance integrated circuit package is disclosed having a number of design features which increase the performance and manufacturability of the integrated circuit package, and reduce the effects of parasitic noise generated within the package. The metallic layers connecting contact fingers formed on ledges around the periphery of a die cavity area, to their respective package pins are organized such that a ground metallic layer is interposed between each pair of input/output signal metallic layers, and each input/output signal metallic layer is sandwiched between a pair of metallic layers wherein one layer of the pair is connected to a voltage supply and the other layer of the pair is connected to a corresponding ground reference.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: April 29, 1997
    Assignee: VLSI Technology, Inc.
    Inventors: Chin-Ching Huang, Sang S. Lee, Ramachandra A. Rao, Fernand N. Forcier, Jr.