Abstract: Technology described herein provides an improved system architecture for offloading infrastructure tasks using a multi-root switch with logic to route, via a switch, application data in a data transfer message between a physical storage device and a host system, the host system interfacing with a virtual function of an IPU, by remapping a transaction identifier field in the data transfer message between a first transaction identifier associated with the virtual function and a second transaction identifier associated with the physical storage device, where the physical storage device is managed by the IPU, and where to route the application data between the host system and the physical storage device includes to bypass temporary storage of the application data in a memory local to the IPU. In some examples a remapping table holds the first transaction identifier and the second transaction identifier.

Abstract: Systems, apparatuses, and methods provide for memory management. Communications with a network interface device are paced to provide memory management. An incoming message is received, via the network interface device, including a hint from a processor of a server via a bi-directional stream. The hint includes buffer space type data and/or buffer space available data. A transfer rate of outgoing messages communicated via the bi-directional stream is adjusted in response to the hint, via the network interface device.

Abstract: Apparatus and method for role-based register protection. For example, one embodiment of an apparatus comprises: one or more processor cores to execute instructions and process data, the one or more processor cores to execute one or more security instructions to protect a virtual machine or trusted application from a virtual machine monitor (VMM) or operating system (OS); an interconnect fabric to couple the one or more processor cores to a device; and security hardware logic to determine whether to allow a read or write transaction directed to a protected register to proceed over the interconnect fabric, the security hardware logic to evaluate one or more security attributes associated with an initiator of the transaction to make the determination.

Abstract: Device virtualization techniques can enable physical I/O devices (such as PCIe devices or other I/O devices) to appear as virtual I/O devices, while also enabling selective exposure of information regarding the physical I/O devices to enable the native drivers of the physical I/O devices to be run. In one example, one or more physical I/O devices associated with a virtual I/O device are locked, and an interface is monitored for requests to those physical I/O devices. The device can be unlocked in response to a request to a predetermined address. When a physical I/O device is locked, read requests to read an identifier of the physical device are blocked, and a value associated with the virtual I/O device is provided. When the physical I/O device is unlocked, read requests to read an identifier of the physical I/O device are forwarded to the physical I/O device.

Abstract: Aspects of the disclosure are directed to systems, methods, and devices that include an application processor. The application processor includes an interface logic to interface with a communication module using a bidirectional interconnect link compliant with a peripheral component interconnect express (PCIe) protocol. The interface logic to receive a data packet from across the link, the data packet comprises a header and data payload; determine a hint bit set in the header of the data packet; determine a steering tag value in the data packet header based on the hint bit set; and transmit the data payload to non-volatile memory based on the steering tag set in the header.

Abstract: Aspects of the disclosure are directed to systems, methods, and devices that include an application processor. The application processor includes an interface logic to interface with a communication module using a bidirectional interconnect link compliant with a peripheral component interconnect express (PCIe) protocol. The interface logic to receive a data packet from across the link, the data packet comprises a header and data payload; determine a hint bit set in the header of the data packet; determine a steering tag value in the data packet header based on the hint bit set; and transmit the data payload to non-volatile memory based on the steering tag set in the header.