Abstract: A receiver in a data read channel has an input terminal for receiving an input signal provided by a transmitter of the data read channel, and produces an output signal at an output terminal. The receiver includes a finite impulse response (FIR) filter coupled to the input terminal and having filter coefficients capable of being adapted, an interpolated timing-recovery circuit coupled to an output of the FIR filter, the timing-recovery circuit having an output signal coupled to the output terminal of the receiver, and a timer circuit coupled to the output terminal and feedback connected to the timing-recovery circuit, wherein the coefficients of the timing-recovery circuit are dynamically adapted using a cost weighted function through a signal power spectrum of the data read channel.

Abstract: A system for decoding digital signals subjected to block coding includes a post-processor that corrects the codewords affected by error, identifying them with the most likely sequence that is a channel sequence and that satisfies a syndrome check. The post-processor is a finite-state machine described by a graph that represents the set of error events. The post-processor evolves in steps through subsequent transition matrices, deleting at each step the paths that accumulate an invalid number of error events or an excessive number of wrong bits, paths that accumulate a total reliability higher than a given threshold, paths with an invalid check on the received sequence, and paths that reveal an invalid syndrome after having reached a maximum number of events.

Abstract: An effective organization and transferring of data among the functional blocks of an integrated system of a read channel of data recorded on DVD-Rom, DVD-Ram, DVD-R or CD Rom for performing Reed-Solomon decoding including off-line heroic correction, or deinterleaving, Reed-Solomon decoding is provided. The integrated system includes an input buffer, an interface with a microcontroller bus, a Reed-Solomon decoder, an embedded RAM accessed through a 17-bit bus, a descrambling and EDC control block for DVD modes of operation, a descrambling block for CD codes of operations, a data output interface, and a timing control block. The system permits the de coding of the input data acquired through the input buffer at a rate of up to four-times the reference bit rate of DVD formatted data using a clock for accessing the embedded RAM having a frequency half that of the clock that is used in the Reed-Solomon decoder, while reducing the number of accesses to the embedded RAM needed to perform the decoding.

Abstract: A method and apparatus for detecting and correcting errors in a magnetic recording channel of a mass storage system that combines a Soft Output Viterbi Algorithm SOVA, which has the capability of detecting the reliability of a discrete, equalized signal, and a post processor, which has the capability of detecting specific error events in said discrete, equalized signal, so as to correct error events and to generate an output bit stream.

Abstract: A system For decoding digital signals subjected to block coding comprising a post-processor which corrects the codewords affected by error, identifying them with the most likely sequence which is a channel sequence and which satisfies a syndrome check. The post-processor is a finite-state machine described by a graph which represents the set of error events, the set of respective transitions defining the structure of said set of error events. Preferably, the post-processor evolves in steps through subsequent transition matrices, deleting at each step the paths which accumulate an invalid number of error events or an excessive number of wrong bits, paths which accumulate a total reliability higher than a given threshold, paths with a invalid check on the received sequence, and paths which reveal an invalid syndrome after having reached a maximum number of events.

Abstract: Signals that are to be transferred, i.e., written and/or read, with respect to the sectors of a storage medium, such as a hard disk, are encoded by using at least two error-correction codes. Two error-correction codes (ECCs) are used of the Reed Solomon type, namely an inner code and an outer code. At the encoded level, the user data are organized in a matrix structure comprising a first set of data sectors (e.g., sixteen data sectors) and are encoded, respectively, by means of the inner code in the horizontal direction of the matrix and by means of the outer code in the vertical direction of the matrix. The redundancy of the outer code is organized in a second set of redundancy sectors, which comprises, for example, two redundancy sectors, written and/or read with respect to said storage medium as the sectors of said first set.

Abstract: A receiver in a data read channel has an input terminal for receiving an input signal provided by a transmitter of the data read channel, and produces an output signal at an output terminal. The receiver includes a finite impulse response (FIR) filter coupled to the input terminal and having filter coefficients capable of being adapted, an interpolated timing-recovery circuit coupled to an output of the FIR filter, the timing-recovery circuit having an output signal coupled to the output terminal of the receiver, and a timer circuit coupled to the output terminal and feedback connected to the timing-recovery circuit, wherein the coefficients of the timing-recovery circuit are dynamically adapted using a cost weighted function through a signal power spectrum of the data read channel.

Abstract: System for decoding code words in the EFM-PLUS and/or EFM format in which an enumeration block makes it possible to associate in a one-to-one manner with each of the code words a numerical value from a practically continuous set of numerical values. The numerical value, possibly summed with an offset value, by an address generator, addresses a read-only memory in which are stored information codes, each of which is associated, as decoded information, with one of the code words.