Abstract: A real time memory address translation device is described herein. The address translation device operates to change memory addresses from one address space that is used by system buses to another address space that is used by a main memory of the associated system. The translation device may be placed on the same chip as a corresponding processor core, for example, on a system on chip. The on-chip arrangement of the translation device enables predictable translation times to meet real-time requirement of time-sensitive subsystems.

Abstract: A system and method for securing a hypervisor and operating systems that execute on a computing device. An encrypted hypervisor is uploaded to a hardware chip. Prior to being executed, the hypervisor is decrypted using a secure security processor and stored in an on-chip memory. When a processor on the hardware chip executes the hypervisor, at least one on-chip component continuously authenticates the hypervisor during execution. A hypervisor configures a processor with access rights associated with an operating system, where the access rights determine access of the operating system to an at least one resource. A transaction filter then uses the access rights associated with the operating system to monitor the access of the operating system to the at least one resource in real-time as the operating system executes on a processor.

Abstract: A device for decoupling audio-video (AV) traffic processing from non-AV traffic processing may include a first processor and a second processor. The first processor may be configured to establish a network connection with a client device, determine whether the network connection is associated with AV traffic, transfer the network connection to a second processor when the network connection is associated with AV traffic, and process non-AV traffic associated with the network connection when the network connection is not associated with AV traffic. The second processor may be configured to receive the network connection from the first processor and process the AV traffic associated with the network connection.

Abstract: A real time memory address translation device is described herein. The address translation device operates to change memory addresses from one address space that is used by system buses to another address space that is used by a main memory of the associated system. The translation device may be placed on the same chip as a corresponding processor core, for example, on a system on chip. The on-chip arrangement of the translation device enables predictable translation times to meet real-time requirement of time-sensitive subsystems.

Abstract: A system for efficient memory bandwidth utilization may include a depacketizer, a packetizer, and a processor core. The depacketizer may generate header information items from received packets, where the header information items include sufficient information for the processor core to process the packets without accessing the payloads from off-chip memory. The depacketizer may accumulate multiple payloads and may write the multiple payloads to the off-chip memory in a single memory transaction when a threshold amount of the payloads have been accumulated. The processor core may receive the header information items and may generate a single descriptor for accessing multiple payloads corresponding to the header information items from the off-chip memory. The packetizer may generate a header for each payload based at least on on-chip information and without accessing off-chip memory. Thus, the subject system provides efficient memory bandwidth utilization, e.g.

Abstract: A system for presentation timing based audio video (AV) stream processing may include a switch device, a first processor, and a second processor. The switch device may be configured to route AV traffic to the first processor for processing and non-AV traffic to the second processor for processing. The first processor may receive transport stream packets that include an audio stream and/or a video stream. The first processor may receive a request to modify presentation timing of the audio stream and/or video stream. The first processor may modify the transport stream packets and/or presentation timing parameters of the transport stream packets based at least in part on the received request. The first processor may provide the transport stream packets to an electronic device. In some implementations, the second processor may be unable to access the content of the transport stream packets in the clear, e.g. due to security considerations.

Abstract: A method of handling retransmission and memory consumption tracking of data packets includes storing data packets from different data channels in respective transmitter ring buffers allocated to the data channels when the data packets are not marked for retransmission, and facilitating retransmission of data packets from a specified ring buffer corresponding to a retransmission sequence number. The method also may include storing received data packets out of sequence in respective receiver ring buffers, marking a descriptor indicating a tail location of the stored data packets, and reclaiming memory space in the ring buffer based on the marked descriptor. The method may include storing a payload address associated with received data packets, marking a descriptor associated with the payload address to indicate the stored data packets have been consumed for processing, and reclaiming memory space when a register contains an indication of the stored payload address based on the marked descriptor.

Abstract: A system and method for securing a hypervisor and operating systems that execute on a computing device. An encrypted hypervisor is uploaded to a hardware chip. Prior to being executed, the hypervisor is decrypted using a secure security processor and stored in an on-chip memory. When a processor on the hardware chip executes the hypervisor, at least one on-chip component continuously authenticates the hypervisor during execution. A hypervisor configures a processor with access rights associated with an operating system, where the access rights determine access of the operating system to an at least one resource. A transaction filter then uses the access rights associated with the operating system to monitor the access of the operating system to the at least one resource in real-time as the operating system executes on a processor.

Abstract: A system for efficient memory bandwidth utilization may include a depacketizer, a packetizer, and a processor core. The depacketizer may generate header information items from received packets, where the header information items include sufficient information for the processor core to process the packets without accessing the payloads from off-chip memory. The depacketizer may accumulate multiple payloads and may write the multiple payloads to the off-chip memory in a single memory transaction when a threshold amount of the payloads have been accumulated. The processor core may receive the header information items and may generate a single descriptor for accessing multiple payloads corresponding to the header information items from the off-chip memory. The packetizer may generate a header for each payload based at least on on-chip information and without accessing off-chip memory. Thus, the subject system provides efficient memory bandwidth utilization, e.g.

Abstract: A system for presentation timing based audio video (AV) stream processing may include a switch device, a first processor, and a second processor. The switch device may be configured to route AV traffic to the first processor for processing and non-AV traffic to the second processor for processing. The first processor may receive transport stream packets that include an audio stream and/or a video stream. The first processor may receive a request to modify presentation timing of the audio stream and/or video stream. The first processor may modify the transport stream packets and/or presentation timing parameters of the transport stream packets based at least in part on the received request. The first processor may provide the transport stream packets to an electronic device. In some implementations, the second processor may be unable to access the content of the transport stream packets in the clear, e.g. due to security considerations.

Abstract: A system for pipelined encryption and packetization of audio video (AV) data may consecutively encrypt a number of AV data units based on a security mechanism, associate the encrypted AV data units with a security header, where the security header is generated before the AV data units are encrypted, and the security header includes information related to the security mechanism, generate network packets for transporting the encrypted AV data units and the associated security header based at least in part on an order in which the AV data units are encrypted, where one or more of the network packets is generated contemporaneous with encrypting one or more of the AV data units, and provide the network packets for transport to a client device as the packets are generated, where the AV data units are encrypted and the network packets are generated without accessing memory external to the system.

Abstract: A device for decoupling audio-video (AV) traffic processing from non-AV traffic processing may include a first processor and a second processor. The first processor may be configured to establish a network connection with a client device, determine whether the network connection is associated with AV traffic, transfer the network connection to a second processor when the network connection is associated with AV traffic, and process non-AV traffic associated with the network connection when the network connection is not associated with AV traffic. The second processor may be configured to receive the network connection from the first processor and process the AV traffic associated with the network connection.

Abstract: A method of handling retransmission and memory consumption tracking of data packets includes storing data packets from different data channels in respective transmitter ring buffers allocated to the data channels when the data packets are not marked for retransmission, and facilitating retransmission of data packets from a specified ring buffer corresponding to a retransmission sequence number. The method also may include storing received data packets out of sequence in respective receiver ring buffers, marking a descriptor indicating a tail location of the stored data packets, and reclaiming memory space in the ring buffer based on the marked descriptor. The method may include storing a payload address associated with received data packets, marking a descriptor associated with the payload address to indicate the stored data packets have been consumed for processing, and reclaiming memory space when a register contains an indication of the stored payload address based on the marked descriptor.

Abstract: A technique to provide hardware protection for bus accesses for a processor in a multiple processor environment where at least two zones are established to separate or segregate processor functionality. In one implementation, control registers within a cache memory that supports the multiple processors are loaded with addresses associated with access rights for a particular processor. Then, when an access request is generated, the registers are checked to authorize the access.

Abstract: A technique to provide ownership tracking of data assets in a multiple processor environment. Ownership tracking allows a data asset to be identified to a particular processor and tracked as the data asset travels within a system or sub-system. In one implementation, the sub-system is a cache memory that provides cache support to multiple processors. By utilizing flag bits attached to the data asset, ownership identification is attached to the data asset to identify which processor owns the data asset.