Abstract: A power output circuit is provided which is protected against latching due to voltage pulses developed by an inductive load. The circuit comprises a transistor constructed on a monolithic integrated circuit chip including a grounded semiconductor substrate of one type conductivity, and including collector and emitter regions of opposite type conductivity located on the substrate and containing opposite type conductivity modifiers. The collector and emitter regions are separated by a base region of one type conductivity, and the collector region is coupled to the inductive load. A fourth region of one type conductivity, containing one type conductivity modifiers is located on the substrate in galvanic contact with the collector region. A resistive impedance is coupled between the fourth region and a source of reference potential, and a capacitor is coupled between the fourth region and the source of reference potential.