Abstract: An integrated circuit comprises a first conductive lines and second lines as well as contact structures being in contact with the first and second conductive lines. The first conductive lines are arranged in a first metallization level, and second conductive lines are arranged in a second metallization level arranged above the first metallization level. The second conductive lines are arranged above the contact structures, and a pitch of neighboring contact structures is equal to a pitch of neighboring second conductive lines. The distance between neighboring contact structures is smaller than 100 nm.

Abstract: A method of forming an integrated circuit having a capacitor is disclosed. In one embodiment, the method includes forming a capacitor element with a first electrode, a dielectric layer and a second electrode. The capacitor element is formed using a support layer.

Abstract: An integrated circuit memory with clock-controlled memory access includes at least one data connection to input/output data, a memory cell array including memory cells to store data, a clock generator circuit to generate a clock signal, a memory circuit to store data, a control circuit to control storage of data in the memory circuit and to control output of data from the memory circuit. The memory circuit is connected to the memory cell array and to the at least one data connection. During read access to the memory cells, first and second data supplied to the memory circuit from the memory cell array are buffer-stored in the memory circuit upon first and second edges of the clock signal. The first and second data are output from the memory circuit and supplied to the at least one data connection upon third and fourth edges of the clock signal.

Abstract: An integrated circuit comprises a first conductive lines and second lines as well as contact structures being in contact with the first and second conductive lines. The first conductive lines are arranged in a first metallization level, and second conductive lines are arranged in a second metallization level arranged above the first metallization level. The second conductive lines are arranged above the contact structures, and a pitch of neighboring contact structures is equal to a pitch of neighboring second conductive lines. The distance between neighboring contact structures is smaller than 100 nm.

Abstract: A memory component comprises a plurality of bit lines, on which memory cells are arranged, and a plurality of sense amplifiers, which are arranged in a row, each sense amplifier being connected to two bit lines. A bit line which is connected to a first sense amplifier in the row is arranged directly adjacent to a bit line which is connected to a second sense amplifier in the same row.

Abstract: A method of forming an integrated circuit having a capacitor is disclosed. In one embodiment, the method includes forming a capacitor element with a first electrode, a dielectric layer and a second electrode. The capacitor element is formed using a support layer.

Abstract: The source area (3) is highly doped, like the channel area, for the same conductance type. The drain area (4) is doped for the opposite conductance type. This results in a saving of area since the source connection (S) can at the same time be used as the well connection or substrate connection.

Abstract: An integrated circuit memory with clock-controlled memory access includes at least one data connection to input/output data, a memory cell array including memory cells to store data, a clock generator circuit to generate a clock signal, a memory circuit to store data, a control circuit to control storage of data in the memory circuit and to control output of data from the memory circuit. The memory circuit is connected to the memory cell array and to the at least one data connection. During read access to the memory cells, first and second data supplied to the memory circuit from the memory cell array are buffer-stored in the memory circuit upon first and second edges of the clock signal. The first and second data are output from the memory circuit and supplied to the at least one data connection upon third and fourth edges of the clock signal.

Abstract: A semiconductor memory device comprises a temperature dependent voltage source for outputting a voltage at its output in dependence on a temperature measured in the semiconductor memory device. At least one memory cell is provided with at least one first transistor. The first transistor includes a first transistor body, which is connected to the output of said temperature dependent voltage source.

Abstract: Methods and systems for the determination of the function and of the position information of fuses from a schematic and/or a network list and a layout. A repair process is aided with this position information.

Abstract: An electronic component has a first bit line and a second bit line, which are coupled to a plurality of memory cells, a line for providing a precharging potential, a resistance component which is connected to the line, a first switch which is coupled between the resistance component and the first bit line for connection of the first bit line to the resistance component, and a second switch, which is coupled between the resistance component and the second bit line, for connection of the second bit line to the resistance component. The electrical resistance of the resistance component is controllable in order to assume a predetermined first resistance value or a predetermined second resistance value which is higher than the first resistance value.

Abstract: A memory component comprises a plurality of bit lines, on which memory cells are arranged, and a plurality of sense amplifiers, which are arranged in a row, each sense amplifier being connected to two bit lines. A bit line which is connected to a first sense amplifier in the row is arranged directly adjacent to a bit line which is connected to a second sense amplifier in the same row.

Abstract: The invention proposes an apparatus for writing to and/or reading from a memory cell in a semiconductor memory having a selection transistor and a storage capacitor, where the apparatus has a device which is used to influence a threshold voltage for the selection transistor contrary to the influence of an ambient temperature. The invention also proposes a method for writing to and/or reading from a memory cell in a semiconductor memory having a selection transistor and a storage capacitor, where the method comprises the following method steps: a) an ambient temperature for the memory cell is ascertained, and b) an electrical voltage is applied to a substrate well in the selection transistor as a function of the ascertained ambient temperature such that a threshold voltage for the selection transistor is influenced contrary to the influence of an ambient temperature.

Abstract: The invention relates to a method for reducing the current consumption of an electronic circuit having at least one test module for testing the electronic circuit. The test module is connected to at least one line and/or a connection of the electronic circuit. A test control signal is generated, by means of which the test module is at least partially decoupled from the line or the connection in an operating mode of the electronic circuit such that switching currents are prevented in the test module.

Abstract: Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit are provided. One embodiment provides a method for addressing memory areas in a memory circuit with successive addresses, with either a regular memory area or a redundant memory area being addressed depending on the address, with an inactive state of a deactivation signal being set when addressing the regular memory area, which inactive state allows the addressing of the regular memory area, with the addressing of the regular memory area being blocked on the basis of an active state of the deactivation signal when addressing the redundant memory area, wherein a change is made from the active state of the deactivation signal to the inactive state of the deactivation signal before the application of the next address for addressing one of the memory areas.

Abstract: A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.

Abstract: Address decoding circuit and method for addressing a regular memory area and a redundant memory area in a memory circuit are provided. One embodiment provides a method for addressing memory areas in a memory circuit with successive addresses, with either a regular memory area or a redundant memory area being addressed depending on the address, with an inactive state of a deactivation signal being set when addressing the regular memory area, which inactive state allows the addressing of the regular memory area, with the addressing of the regular memory area being blocked on the basis of an active state of the deactivation signal when addressing the redundant memory area, wherein a change is made from the active state of the deactivation signal to the inactive state of the deactivation signal before the application of the next address for addressing one of the memory areas.

Abstract: A conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.

Abstract: The invention discloses a method for the chemical-mechanical polishing of layers composed of metals of the group of platinum metals, particularly iridium. In the CMP process, high erosion rates for iridium and a high selectivity relative to silicon oxide are achieved upon employment of a polishing fluid that contains 1 through 6% by weight abrasive particles, 2 through 20% by weight of at least one oxidation agent selected from the group comprising Ce(IV) salts, salts of chloric acid, salts of peroxodisulfuric acid, hydrogen peroxide and salts of hydrogen peroxide, and 74 through 97% by weight water. This enables the structuring of iridium layers with the assistance of an oxide mask and a CMP process.

Abstract: The integrated circuit has a test circuit, which is connected to an input terminal of the integrated circuit via a line connection. An isolating device is provided between an input terminal of the test circuit in order to completely isolate the line connection between the test circuit and the input terminal after the test circuit has performed a test procedure.