Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform an erase operation and in response to the command to perform the erase operation, begin execution of the erase operation. The controller might be further configured to while executing the erase operation, receive a command to perform a program operation; in response to the command to perform the program operation, suspend the execution of the erase operation; and with the execution of the erase operation suspended, execute the program operation.

Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform a program operation and in response to the command to perform the program operation, begin execution of the program operation. The controller might be further configured to while executing the program operation, receive a command to perform a read operation; in response to the command to perform the read operation, suspend the execution of the program operation; and with the execution of the program operation suspended, execute the read operation.

Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform an erase operation; and in response to the command to perform the erase operation, begin execution of the erase operation. The controller might be further configured to while executing the erase operation, receive a command to perform a program operation; in response to the command to perform the program operation, suspend the execution of the erase operation; and with the execution of the erase operation suspended, execute the program operation.

Abstract: Driver circuits are described for driving one or more light emitting diodes. A driver circuit may comprise an interface configured to receive control signals from a processor and a signal generator configured to generate pulse modulation (PM) signals based on the control signals, wherein the PM signals define phase shifts. In some examples, the signal generator is configured to: determine whether the control signals indicate a phase shift change; and in response to determining that the control signals indicate a phase shift change, terminate a current PM signal at a beginning of a PM period, and generate a new PM signal in the PM period, wherein the new PM signal includes the phase shift change. In other examples, termination may be avoided in some situations, for example, upon determining that a new phase shift is not sufficiently less than a previous phase shift.

Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform a program operation and in response to the command to perform the program operation, begin execution of the program operation. The controller might be further configured to while executing the program operation, receive a command to perform a read operation; in response to the command to perform the read operation, suspend the execution of the program operation; and with the execution of the program operation suspended, execute the read operation.

Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform an erase operation; and in response to the command to perform the erase operation, begin execution of the erase operation. The controller might be further configured to while executing the erase operation, receive a command to perform a program operation; in response to the command to perform the program operation, suspend the execution of the erase operation; and with the execution of the erase operation suspended, execute the program operation.

Abstract: A circuit for filtering glitches that corrupt a digital input signal includes an enable path input with the digital signal and a reset signal. The enable path generates a corresponding active output signal when the reset signal is null and the digital signal assumes a logic active value, or a null output signal when the reset signal is asserted. The circuit also includes a delay line producing an internal signal as delayed replica of the output signal. The circuit further includes a disable path enabled or disabled by the internal signal, which receives the digital signal and, when enabled, asserts the reset signal when the digital signal becomes null.

Abstract: A circuit for filtering glitches that corrupt a digital input signal includes an enable path input with the digital signal and a reset signal. The enable path generates a corresponding active output signal when the reset signal is null and the digital signal assumes a logic active value, or a null output signal when the reset signal is asserted. The circuit also includes a delay line producing an internal signal as delayed replica of the output signal. The circuit further includes a disable path enabled or disabled by the internal signal, which receives the digital signal and, when enabled, asserts the reset signal when the digital signal becomes null.