Patents by Inventor Floyd Eide

Floyd Eide has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7242082
    Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: July 10, 2007
    Assignee: Irvine Sensors Corp.
    Inventor: Floyd Eide
  • Publication number: 20060055039
    Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.
    Type: Application
    Filed: September 15, 2005
    Publication date: March 16, 2006
    Inventor: Floyd Eide
  • Patent number: 4956694
    Abstract: A device for increasing the density of integrated circuit chips on a printed circuit board. A plurality of integrated circuits are packaged within chip carriers and stacked, on one top of the other, on a printed circuit board. Each of the input/output data terminals, power and ground terminals of the chips are connected in parallel. Each chip is individually accessed by selectively enabling the desired chip.
    Type: Grant
    Filed: November 4, 1988
    Date of Patent: September 11, 1990
    Assignee: Dense-Pac Microsystems, Inc.
    Inventor: Floyd Eide
  • Patent number: RE43536
    Abstract: Layers suitable for stacking in three dimensional, multilayer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are underfilled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: July 24, 2012
    Assignee: Aprolase Development Co., LLC
    Inventor: Floyd Eide