Abstract: A process for fabricating multi-level semiconductor ROM devices is disclosed. Each memory cell of the ROM device can be programmed to any of three possible conduction states including full-conduction, half-conduction and no-conduction. The fabrication process begins with a semiconductor silicon substrate. Buried bit and word lines are formed in the substrate. A photomask is then formed to correspond to code to be programmed into the ROM device. The photomask, when properly aligned over the ROM device, contains portions that fully cover the entire channel region of a cell to be programmed for full conduction, portions that partially cover the channel regions of cells that are to be programmed for half-conduction, and portions that do not cover at all the channel regions of cells to be programmed for no-conduction. Then ions are implanted with the photomask in place. The ions transform the regions not covered or partially covered by the photomask.

Abstract: A decoding method for tri-state read-only memory is disclosed herein. The cells of the tri-state memory are read the storage bits of all cells are combined to form a storage code. Each bit represents one of a first state, a second state and a third state. The storage code is first decoded to convert the storage code into an intermediate code. The intermediate code includes a plurality of conversion codes, each of which is one of a first code, a second code, and a third code corresponding respectively to the first, second, and third states. The intermediate code is further decoded into the binary output code. The resulting binary code has a greater number of bits than its corresponding storage code. Thus, the read-only memory, in accordance with the present invention, can store more than one bit of data in a single memory cell.

Abstract: A multi-stage sense amplifier for read-only memory having a memory array consisting of a large number of memory cell units. The sense amplifier includes a sense amplifier for sensing the currents flowing through the transistor of the memory cell units of the read-only memory. The memory cell unit transistors are programmed with one of four current capacity characteristics. The sense amplifier also includes three current comparators coupled to the sense amplifier, with each of the comparators having a current comparing unit for comparing the sensed current flowing through the memory cell unit transistors to the current flowing through the comparators. An output of each of the three comparators is provided for identifying whether or not the current of a four capacity characteristics flowing through the memory cell unit transistors is larger than the current flowing through the comparator.

Abstract: A late programming mask ROM integrated circuit and a process for producing the same. The mask ROM integrated circuit has a silicon substrate, and a plurality of memory cells formed on the silicon substrate. Each memory cell consists of a transistor element and a diode element electrically connected in series. Each transistor element has a drain layer, a channel layer, a source layer all stacked on the silicon substrate in a substantially vertical direction to form an upright drain/channel/source structure region, and a gate electrode region formed on the silicon substrate. The gate electrode regions and the upright drain/channel/source structure regions of the transistor elements are alternately arranged in an adjacent fashion along a substantially horizontal direction. Each diode element is formed by one upright drain/channel/source structure and a diode layer formed on or under the upright drain/channel/source structure.

Abstract: A late programming mask ROM integrated circuit and a process for producing the same. The mask ROM integrated circuit has a silicon substrate, and a plurality of memory cells formed on the silicon substrate. Each memory cell consists of a transistor element and a diode element electrically connected in series. Each transistor element has a drain layer, a channel layer, a source layer all stacked on the silicon substrate in a substantially vertical direction to form an upright drain/channel/source structure region, and a gate electrode region formed on the silicon substrate. The gate electrode regions and the upright drain/channel/source structure regions of the transistor elements are alternately arranged in an adjacent fashion along a substantially horizontal direction. Each diode element is formed by one upright drain/channel/source structure and a diode layer formed on or under the upright drain/channel/source structure.