Patents by Inventor Fong Lim
Fong Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11520526Abstract: A write method for a resistive memory including a storage array, a control circuit and an access circuit is provided. The control circuit receives an external command to activate the access circuit to access the storage array. The write method includes determining whether the external command is ready to perform a write operation for the storage array; generating a first operation voltage group to the access circuit when the external command does not perform the write operation for the storage array; reading a count value of a block that corresponds to a write address when the external command performs the write operation for the storage array, wherein the count value indicates the number of times that the block corresponding to the write address performs the write operation; and generating a second operation voltage group to the access circuit according to the count value of the block.Type: GrantFiled: June 2, 2021Date of Patent: December 6, 2022Assignee: WINBOND ELECTRONICS CORP.Inventors: Ping-Kun Wang, Shao-Ching Liao, Chien-Min Wu, Chia Hua Ho, Frederick Chen, He-Hsuan Chao, Seow-Fong Lim
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Publication number: 20220374079Abstract: According to various embodiments, a display device may be provided. The display device may include: a receiver configured to receive user data based on an electroencephalography measurement; at least one light source; and a controller configured to control the at least one light source based on the user data.Type: ApplicationFiled: August 5, 2022Publication date: November 24, 2022Inventors: Min-Liang Tan, Kian Sin Yeo, Beng Leong Toh, Ji Fong Lim, Gui Mei Dai, Kah Yong Lee, Aninda Kanti Sen
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Patent number: 11439340Abstract: According to various embodiments, a display device may be provided. The display device may include: a receiver configured to receive user data based on an electroencephalography measurement; at least one light source; and a controller configured to control the at least one light source based on the user data.Type: GrantFiled: June 17, 2016Date of Patent: September 13, 2022Assignee: Razer (Asia-Pacific) Pte. Ltd.Inventors: Min-Liang Tan, Kian Sin Yeo, Beng Leong Toh, Ji Fong Lim, Gui Mei Dai, Kah Yong Lee, Aninda Kanti Sen
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Patent number: 11398256Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.Type: GrantFiled: April 9, 2020Date of Patent: July 26, 2022Assignee: Unity Semiconductor CorporationInventors: Chang Hua Siau, Christophe Chevallier, Darrell Rinerson, Seow Fong Lim, Sri Rama Namala
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Patent number: 11355429Abstract: An electrical interconnect structure includes a bond pad having a substantially planar bonding surface, and a solder enhancing structure that is disposed on the bonding surface and includes a plurality of raised spokes that are each elevated from the bonding surface. Each of the raised spokes has a lower wettability relative to a liquefied solder material than the bonding surface. Each of the raised spokes extend radially outward from a center of the solder enhancing structure.Type: GrantFiled: January 28, 2020Date of Patent: June 7, 2022Assignee: Infineon Technologies AGInventors: Paul Armand Asentista Calo, Tek Keong Gan, Ser Yee Keh, Tien Heng Lem, Fong Lim, Michael Stadler, Mei Qi Tay
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Patent number: 11314588Abstract: A memory device and a multiple cells error correction in a memory cell is provided. The memory device includes a plurality of memory cells and a memory control circuit. Each of the memory cells includes a first type physical cell and a second type physical cell. The memory control circuit is coupled to each of the memory cells. The memory control circuit writes a writing data into the first type physical cell and verifies the data stored in the first type physical cell is same as the writing data or not. The writing data is set and processed by performing a write operation. The memory control circuit writes the writing data into the second type physical cell when the data stored in the first type physical cell is not same as the writing data.Type: GrantFiled: November 11, 2019Date of Patent: April 26, 2022Assignee: Winbond Electronics Corp.Inventors: Chuen-Der Lien, Ming-Huei Shieh, Chi-Shun Lin, Seow Fong Lim, Ngatik Cheung
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Patent number: 11270764Abstract: The invention relates to a two-bit memory cell structure, and an array architecture and a circuit structure thereof in an in-memory computing chip. The double-bit storage unit comprises three transistors which are connected in series, a selection transistor in the middle is used as a switch, and two charge storage transistors are symmetrically arranged on the two sides of the double-bit storage unit. A storage array formed by the double-bit storage unit is used for storing the weight of the neural network, and multiplication and accumulation operation of the neural network is carried out in a two-step current detection mode. According to the invention, leakage current can be effectively controlled, higher weight storage density and higher reliability are realized, and neural network operation with more practical significance is further realized.Type: GrantFiled: July 1, 2021Date of Patent: March 8, 2022Assignee: NANJING UCUN TECHNOLOGY INCInventors: Wei Cong, Seow Fong Lim
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Publication number: 20220005525Abstract: The invention relates to a two-bit memory cell structure, and an array architecture and a circuit structure thereof in an in-memory computing chip. The double-bit storage unit comprises three transistors which are connected in series, a selection transistor in the middle is used as a switch, and two charge storage transistors are symmetrically arranged on the two sides of the double-bit storage unit. A storage array formed by the double-bit storage unit is used for storing the weight of the neural network, and multiplication and accumulation operation of the neural network is carried out in a two-step current detection mode. According to the invention, leakage current can be effectively controlled, higher weight storage density and higher reliability are realized, and neural network operation with more practical significance is further realized.Type: ApplicationFiled: July 1, 2021Publication date: January 6, 2022Inventors: Wei CONG, Seow Fong LIM
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Publication number: 20210286562Abstract: A write method for a resistive memory including a storage array, a control circuit and an access circuit is provided. The control circuit receives an external command to activate the access circuit to access the storage array. The write method includes determining whether the external command is ready to perform a write operation for the storage array; generating a first operation voltage group to the access circuit when the external command does not perform the write operation for the storage array; reading a count value of a block that corresponds to a write address when the external command performs the write operation for the storage array, wherein the count value indicates the number of times that the block corresponding to the write address performs the write operation; and generating a second operation voltage group to the access circuit according to the count value of the block.Type: ApplicationFiled: June 2, 2021Publication date: September 16, 2021Inventors: Ping-Kun WANG, Shao-Ching LIAO, Chien-Min WU, Chia Hua HO, Frederick CHEN, He-Hsuan CHAO, Seow-Fong LIM
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Patent number: 11088711Abstract: The invention provides a data accessing method for a memory apparatus. The data accessing method includes: performing a reading operation on the memory apparatus based on an address information to obtain a codeword and an indicator, where the indicator corresponds to the codeword; enabling a first error correction code (ECC) operation or second ECC operation to be operated on the codeword for generating an error corrected data, wherein, the first ECC operation corrects less bits than the second ECC operation.Type: GrantFiled: July 8, 2019Date of Patent: August 10, 2021Assignee: Winbond Electronics Corp.Inventors: Chuen-Der Lien, Chi-Shun Lin, Seow Fong Lim, Ngatik Cheung
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Publication number: 20210233839Abstract: An electrical interconnect structure includes a bond pad having a substantially planar bonding surface, and a solder enhancing structure that is disposed on the bonding surface and includes a plurality of raised spokes that are each elevated from the bonding surface. Each of the raised spokes has a lower wettability relative to a liquefied solder material than the bonding surface. Each of the raised spokes extend radially outward from a center of the solder enhancing structure.Type: ApplicationFiled: January 28, 2020Publication date: July 29, 2021Inventors: Paul Armand Asentista Calo, Tek Keong Gan, Ser Yee Keh, Tien Heng Lem, Fong Lim, Michael Stadler, Mei Qi Tay
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Patent number: 11069386Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.Type: GrantFiled: May 8, 2020Date of Patent: July 20, 2021Assignee: Unity Semiconductor CorporationInventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau
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Patent number: 11055021Abstract: A resistive memory including a storage array, a storage circuit, a control circuit, a voltage generation circuit and an access circuit is provided. The storage array includes a plurality of blocks. Each block includes a plurality of memory cells. The storage circuit stores a plurality of count values. Each of the count values indicates the number of times that a corresponding block performs a write operation. The control circuit generates a control signal according to the count values when an external command is a write command. The voltage generation circuit provides an operation voltage group according to the control signal. The access circuit accesses the storage array according to the operation voltage group.Type: GrantFiled: March 14, 2019Date of Patent: July 6, 2021Assignee: WINBOND ELECTRONICS CORP.Inventors: Ping-Kun Wang, Shao-Ching Liao, Chien-Min Wu, Chia Hua Ho, Frederick Chen, He-Hsuan Chao, Seow-Fong Lim
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Patent number: 11010245Abstract: The disclosure is directed to a memory storage apparatus having a dynamic data repair mechanism. The memory storage apparatus includes a connection interface; a memory array; and a memory control circuit configured at least to: receive, from the connection interface, a write command which includes a user data and an address of the user data; encode the user data as a codeword which includes the user data and parity bits; write the codeword, in a first memory location of the memory array, as a written codeword; perform a read procedure of the written codeword to determine whether the written codeword is erroneously written; and store a redundant codeword of the user data in a second memory location in response to having determined that the written codeword is erroneously written.Type: GrantFiled: June 28, 2019Date of Patent: May 18, 2021Assignee: Winbond Electronics Corp.Inventors: Chuen-Der Lien, Ming-Huei Shieh, Seow-Fong Lim, Ngatik Cheung, Chi-Shun Lin
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Publication number: 20210141689Abstract: A memory device and a multiple cells error correction in a memory cell is provided. The memory device includes a plurality of memory cells and a memory control circuit. Each of the memory cells includes a first type physical cell and a second type physical cell. The memory control circuit is coupled to each of the memory cells. The memory control circuit writes a writing data into the first type physical cell and verifies the data stored in the first type physical cell is same as the writing data or not. The writing data is set and processed by performing a write operation. The memory control circuit writes the writing data into the second type physical cell when the data stored in the first type physical cell is not same as the writing data.Type: ApplicationFiled: November 11, 2019Publication date: May 13, 2021Applicant: Winbond Electronics Corp.Inventors: Chuen-Der Lien, Ming-Huei Shieh, Chi-Shun Lin, Seow Fong Lim, Ngatik Cheung
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Patent number: 10937495Abstract: A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.Type: GrantFiled: July 2, 2019Date of Patent: March 2, 2021Assignee: Winbond Electronics Corp.Inventors: He-Hsuan Chao, Ping-Kun Wang, Seow Fong Lim, Norio Hattori, Chien-Min Wu, Chih-Hua Hung
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Publication number: 20210013906Abstract: The invention provides a data accessing method for a memory apparatus. The data accessing method includes: performing a reading operation on the memory apparatus based on an address information to obtain a codeword and an indicator, where the indicator corresponds to the codeword; enabling a first error correction code (ECC) operation or second ECC operation to be operated on the codeword for generating an error corrected data, wherein, the first ECC operation corrects less bits than the second ECC operation.Type: ApplicationFiled: July 8, 2019Publication date: January 14, 2021Applicant: Winbond Electronics Corp.Inventors: Chuen-Der Lien, Chi-Shun Lin, Seow Fong Lim, Ngatik Cheung
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Publication number: 20210005255Abstract: A resistive memory and a method for writing data thereof are provided. The method for writing data includes: receiving a write-in data and generating an inverted write-in data; reading a current data in a plurality of selected memory cells; comparing the current data with the write-in data and the inverted write-in data; selecting the write-in data or the inverted write-in data to generate a final data according to a comparison result; and writing the final data into the selected memory cells.Type: ApplicationFiled: July 2, 2019Publication date: January 7, 2021Applicant: Winbond Electronics Corp.Inventors: He-Hsuan Chao, Ping-Kun Wang, Seow Fong Lim, Norio Hattori, Chien-Min Wu, Chih-Hua Hung
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Patent number: 10853167Abstract: The invention provides a memory apparatus including a memory cell array and a hierarchical error correction code (ECC) layer. The hierarchical ECC layer, includes N layers of ECC coder-decoder, wherein the hierarchical ECC layer enables one of the N layers to operate an encoding or decoding operation on processed data, and the hierarchical ECC layer enables another one of the N layers merely when the error bit number of the processed data reaches to N?1 pre-set error correction number(s), and N is a positive integer larger than 1.Type: GrantFiled: January 28, 2019Date of Patent: December 1, 2020Assignee: Winbond Electronics Corp.Inventors: Chuen-Der Lien, Ming-Huei Shieh, Chi-Shun Lin, Seow Fong Lim, Ngatik Cheung
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Publication number: 20200335144Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.Type: ApplicationFiled: May 8, 2020Publication date: October 22, 2020Inventors: Christophe Chevallier, Seow Fong Lim, Chang Hua Siau