Abstract: In a computer system, one or more ISA connector sockets is replaced by a connector structure which carries both ISA signals and local bus signals. The connector structure is arranged such that a standard ISA accessory card may be inserted, in which case only ISA signals are coupled to or from the card. "Local bus" accessory cards may also be designed for insertion into such a connector, and these cards may connect to one or more signal lines of the local bus either additionally or instead of connections made to the ISA bus. By physical or other means, ISA accessory cards are prevented from unintentional contact with connector contacts which are coupled to local bus signal lines. The connector structure may advantageously comprise an EISA-type connector socket.

Abstract: According to the invention, a chipset is provided which powers up in a default state with caching disabled and which writes permanently non-cacheable tags into tag RAM entries corresponding to memory addresses being read while caching is disabled. Even though no "valid" bit is cleared, erroneous cache hits after caching is enabled are automatically prevented since any address which does match a tag in the tag RAM, is a non-cacheable address and will force retrieval directly from main memory anyway.

Abstract: In an IBM PC AT-compatible computer architecture, CPU-generated addresses and data for accesses to a peripheral device in the I/O address space are coupled directly to the peripheral device from the local bus, without traversing the I/O bus. Any data returned from the peripheral device is coupled directly to the local bus, also without traversing the I/O bus. No buffers are needed for communicating such address and data information between the peripheral device and the I/O bus.

Abstract: According to the invention, a chipset is provided which powers up in a default state with cacheing disabled and which writes permanently non-cacheable tags into tag RAM entries corresponding to memory addresses being read while cacheing is disabled. Even though no "valid" bit is cleared, erroneous cache hits after cacheing is enabled are automatically prevented since any address which does match a tag in the tag RAM, is a non-cacheable address and will force retrieval directly from main memory anyway. Two cache tag test modes are also described, as is a cache sizing algorithm.