Abstract: The present invention relates in general to the field of integrated circuits, and more specifically to a meander resistor. Basically, a meander resistor can be considered as a bar resistor with the exception of the corner squares (right-angle bends). The Electrostatic Discharge (ESD) sensitivities of on-chip resistors can be a problem for both electronic manufactures and electronic component users. As others components, passive devices are known to be susceptible to ESD events. The context of this invention is to improve the reliability of the resistors during an ESD event. An ESD stress means that high current and high voltage levels are applied to the device. The device has to be able to dissipate this energy without failure.

Abstract: The present invention relates in general to the field of integrated circuits, and more specifically to a meander resistor. Basically, a meander resistor can be considered as a bar resistor with the exception of the corner squares (right-angle bends). The Electrostatic Discharge (ESD) sensitivities of on-chip resistors can be a problem for both electronic manufactures and electronic component users. As others components, passive devices are known to be susceptible to ESD events. The context of this invention is to improve the reliability of the resistors during an ESD event. An ESD stress means that high current and high voltage levels are applied to the device. The device has to be able to dissipate this energy without failure.

Abstract: The invention provides an electrostatic discharge (ESD) protection device with an increased capability to discharge ESD generated current with a reduced device area. The ESD protection device comprises a grounded gate MOS transistor (1) with a source region (3) and a drain region (4) of a first semiconductor type interposed by a first well region (7) of a second semiconductor type. Second well regions (6) of the first semiconductor type, interposed by the first well region (7), are provided beneath the source region (3) and the drain region (4). Heavily doped buried regions (8,9) of the same semiconductor types, respectively, as the adjoining well regions (6,7) are provided beneath the well regions (6,7).

Abstract: The invention provides an electrostatic discharge (ESD) protection device with an increased capability to discharge ESD generated current with a reduced device area. The ESD protection device comprises a grounded gate MOS transistor (1) with a source region (3) and a drain region (4) of a first semiconductor type interposed by a first well region (7) of a second semiconductor type. Second well regions (6) of the first semiconductor type, interposed by the first well region (7), are provided beneath the source region (3) and the drain region (4). Heavily doped buried regions (8,9) of the same semiconductor types, respectively, as the adjoining well regions (6,7) are provided beneath the well regions (6,7).