Abstract: A vertical unipolar component formed in a semiconductor substrate, comprising vertical fingers made of a conductive material surrounded with silicon oxide, portions of the substrate being present between the fingers and the assembly being coated with a conductive layer. The component periphery includes a succession of fingers arranged in concentric trenches, separated from one another by silicon oxide only, the upper surface of the fingers of at least the innermost rank being in contact with said conductive layer.

Abstract: The invention relates to a vertical-type single-pole component, comprising regions with a first type of conductivity which are embedded in a thick layer with a second type of conductivity. Said regions are distributed over at least one same horizontal level and are independent of each other.

Abstract: A MOS power component in which the active regions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. A MOS power transistor according to the present invention alternately includes a source region of a first conductivity type, an intermediary region, and a drain region of the first conductivity type, each of these regions extending across the entire thickness of the substrate, the source and drain regions being contacted by conductive fingers or plates substantially crossing the substrate, insulated and spaced apart conductive fingers crossing from top to bottom the intermediary region, the horizontal distance between the insulated fingers being such that the intermediary region can be inverted when an appropriate voltage is applied to these insulated fingers.

Abstract: The invention relates to a vertical-type single-pole component, comprising regions (34) with a first type of conductivity (P) which are embedded in a thick layer (32) with a second type of conductivity (N). Said regions are distributed over at least one same horizontal level and are independent of each other. The regions also underlie an insulating material (70).

Abstract: A vertical unipolar component formed in a semiconductor substrate. An upper portion of the substrate includes insulated trenches filled with a vertical multiple-layer of at least two conductive elements separated by an insulating layer, the multiple-layer depth being at most equal to the thickness of the upper portion.

Abstract: A method of manufacturing a unipolar component of vertical type in a substrate of a first conductivity type, including the steps of: forming trenches in a silicon layer of the first conductivity type; coating the lateral walls of the trenches with a silicon oxide layer; filling the trenches with polysilicon of the second conductivity type; and annealing to adjust the doping level of the polysilicon, the excess dopants being absorbed by the silicon oxide layer.

Abstract: A method for manufacturing a vertical Schottky diode with a guard ring on a lightly-doped N-type silicon carbide layer, comprising the steps of forming a P-type epitaxial layer on the N-type layer; implanting N-type dopants in areas of the P-type epitaxial layer to neutralize in these areas, across the entire thickness of the epitaxial layer, the P-type dopants to form N-type regions, of dopant concentration lower than that of the epitaxial layer, and delimiting a P-type guard ring; forming on the external periphery of the component an insulating layer partially covering the guard ring; and forming a Schottky contact with the N-type region internal to the guard ring.

Abstract: The invention relates to a vertical-type single-pole component, comprising regions (34) with a first type of conductivity (P) which are embedded in a thick layer (32) with a second type of conductivity (N). Said regions are distributed over at least one same horizontal level and are independent of each other. The regions also underlie an insulating material.

Abstract: The present invention relates to a Schottky barrier diode which contains a substrate region of a first conductivity type formed in a semiconductor material layer of same conductivity type and a metal layer. A doped region of a second conductive type is formed in the semiconductor layer, with the doped region disposed under the material layer and separated from other doped regions by portions of the semiconductor layer.