Abstract: An electrical device for high-voltage applications and a method for obtaining an electrical device. The electrical device includes a capacitor having: a bottom electrode having a conductive structure, the conductive structure including a base surface and facing protruding walls extending upwards and having a highest surface; a top electrode having at least one conductive region arranged between the facing protruding walls and having a top surface, wherein the top surface of the at least one conductive region lies below or at the level of the highest surface of the protruding walls; and a dielectric region extending conformally over the bottom electrode and surrounding the top electrode, the capacitor being formed by the bottom and top electrodes separated by the dielectric region.

Abstract: Three-dimensional capacitive structures may be produced by forming a capacitive stack conformally over pores in a region of porous anodic oxide. The porous anodic oxide region is provided on a stack of electrically-conductive layers including an anodization-resistant layer and an interconnection layer. In the pores there is a position having restricted diameter quite close to the pore bottom. In a first percentage of the pores in the region of anodic oxide, a functional portion of the capacitive stack is formed so as to extend into the pores no further than the restricted-diameter position. Cracks that may be present in the anodization-resistant layer have reduced effect on the properties of the capacitive structure. Increased thickness of the anodization-resistant layer can be tolerated, enabling equivalent series resistance of the overall capacitive structure to be reduced.

Abstract: A capacitor structure that includes a silicon substrate having a trench structure formed therein; a dielectric disposed over a surface of the trench structure, conformal to the surface of the trench structure; and a filling layer disposed over the dielectric layer and into the trench structure, the filling layer including a conductive layer and a polymer layer.

Abstract: A supercapacitor that includes: a first electrode; a second electrode; and a composite solid electrolyte disposed between the first electrode and the second electrode. The composite solid electrolyte includes a dielectric matrix and an ionic conductor disposed in channels/pores in the dielectric matrix. Methods of fabricating such supercapacitors are also disclosed.

Abstract: A nanomagnetic inductor core that includes: a porous, electrically-insulating template having high-permeability material in the pores thereof to constitute elongated nanowires, and wherein the elongated nanowires are segmented along their axial direction; and a segment of dielectric material interposed between adjacent segments of the high-permeability material along the axial direction of the nanowire; wherein each segment of the high-permeability material has a length, in the axial direction of the nanowire, no greater than a size of a single magnetic domain, and wherein a maximal cross-sectional dimension of the nanowire is no greater than the size of the single magnetic domain. Inductors and LC interposers using such nanomagnetic inductor cores, as well as associated fabrication methods.

Abstract: A distributed LC filter structure is disclosed. The distributed LC filter structure provides simultaneously a distributed inductance and a distributed capacitance in the same structure. Accordingly, discrete passive elements are eliminated and high, homogenous integration is achieved. Interconnections between the distributed inductance and the distributed capacitance are tailored to leverage a parasitic inductance of the distributed capacitance to increase the overall inductance of the distributed LC filter structure. Similarly, the interconnections are tailored to leverage a parasitic capacitance resulting from the distributed inductance to add up with the distributed capacitance augmenting the overall capacitance of the structure.

Abstract: A method for manufacturing an electrical device that includes: anodizing a portion of an anodizable metal layer so as to obtain an anodic porous oxide region and an anodizable metal region adjoining the anodic porous oxide region, the anodic porous oxide region being thicker than the anodizable metal region; depositing a layer of liner material on the anodic porous oxide region and on the anodizable metal region; depositing a layer of filler material on the layer of liner material to obtain a stacked structure having a top surface; planarizing the stacked structure from a top surface thereof until reaching the layer of the liner material, so as to expose a portion of liner material located above at least a portion of the anodic porous oxide region; and removing the exposed portion of liner material.

Abstract: A method of fabricating a capacitor that includes: forming a three-dimensional structure over a substrate, the three-dimensional structure having a region with elongated pores extending towards the substrate from a top surface of the three-dimensional structure remote from the substrate or elongated columns extending away from the substrate towards the top surface of the three-dimensional structure remote from the substrate; forming a first electrode layer over a surface of the region of the three-dimensional structure, the first electrode conformal to the surface of the region; forming an intermediate layer over the first electrode layer; and forming a second electrode layer over the intermediate layer, the second electrode layer conformal to the intermediate layer, wherein forming the intermediate layer includes: forming a solid-state electrolyte layer partially conformal to the first electrode layer; and forming a dielectric layer conformal to the first electrode layer.

Abstract: A capacitor structure that includes a substrate; a conductive layer above the substrate; and a porous layer, above the conductive layer, having pores that extend perpendicularly from a top surface of the porous layer toward the conductive layer. The porous layer comprises a first region in which pores conductive wires are disposed, and a second region in which pores a metal-insulator-metal (MIM) structure is disposed. The first region may be used as a via to contact a bottom electrode of the capacitor structure.

Abstract: An electrical device that includes: a substrate; an anodic porous oxide region above the substrate; a first capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the first capacitor electrode region having a first wall perpendicular to the top surface; a second capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the second capacitor electrode region having a second wall perpendicular to the top surface and facing the first wall of the first capacitor electrode region, the first wall of the first capacitor electrode region and the second wall of the second capacitor electrode region being separated by a dielectric portion comprising a part of the anodic porous oxide region.

Abstract: A nanowire structure that includes a conductive layer; conductive wires having first ends that contact the conductive layer and second ends that protrude from the conductive layer; and a lateral bridge layer that connects laterally a number of the conductive wires to provide a substantially uniform spacing between the conductive wires.

Abstract: An electrical device that includes: a metal barrier layer; an anodic porous oxide region on the metal barrier layer; a trench around the anodic porous oxide region reaching the metal barrier layer; a liner at least on a wall of the trench on a side of the anodic porous oxide region forming an electrical isolation barrier and having an opening onto the anodic porous oxide region; a hard mask arranged above the trenches and the liner having an opening onto the anodic porous oxide region. A corresponding manufacturing method is also disclosed.

Abstract: A method for manufacturing an electrical device that includes: anodizing a portion of an anodizable metal layer so as to obtain an anodic porous oxide region and an anodizable metal region adjoining the anodic porous oxide region, the anodic porous oxide region being thicker than the anodizable metal region; depositing a layer of liner material on the anodic porous oxide region and on the anodizable metal region; depositing a layer of filler material on the layer of liner material to obtain a stacked structure having a top surface; planarizing the stacked structure from a top surface thereof until reaching the layer of the liner material, so as to expose a portion of liner material located above at least a portion of the anodic porous oxide region; and removing the exposed portion of liner material.

Abstract: A nanowire array structure having an array of nanopillars located in a well in a material layer. The nanopillars of the array extend in the direction from the well floor towards the well mouth. A hard mask overlies the outer peripheral nanopillars in the array and extends outwards to cover the remainder of the well mouth. An aperture in the hard mask exposes the nanopillars disposed inwardly of the outer peripheral nanopillars. The hard mask planarizes the structure, avoiding formation of large topological features at the periphery of the array of nanopillars, thus facilitating integration of the structure into a semiconductor product. At least some of the outer peripheral nanopillars may be in pores of anodic oxide. There are also disclosed semiconductor products incorporating such nanowire array structures and methods of their fabrication.

Abstract: An electronic component comprising a 3D capacitive structure includes a substrate having a contoured surface comprising a plurality of wells extending from the surface into the substrate body, a dielectric formed over, and conforming to the shape of, the contoured surface, and a first electrode formed over the dielectric and conforming to the contoured surface shape. The substrate constitutes a second electrode and the dielectric is interposed between it and the first electrode. Portions of the dielectric are exposed through openings at the base of the contoured surface and contact an insulating layer formed under the substrate, reducing the electrostatic field arising in the contacted portions of the dielectric when a potential difference is applied between the first and second electrodes. The openings at the bottom of the wells are obturated by the dielectric, defining blind holes within the wells, and the first electrode is in the blind holes.

Abstract: A semi-conductor structure with selective bottom terminal contacting is described. The semiconductor device comprises a first metal layer disposed over a substrate; a conductive layer disposed over the first metal layer; and a second metal layer disposed over the conductive layer, the second metal layer embedding a porous structure comprising a plurality of pores that extend substantially perpendicularly from a top surface of the porous structure toward the conductive layer, wherein only a subset of the plurality of pores open onto the conductive layer.

Abstract: An integrated energy storage component that includes a substrate supporting a contoured layer having a region with a contoured surface such as elongated pores. A stack structure is provided conformally over the contoured surface of this region. The stack is a single or repeated instance of MOIM layers, or MIOM layers, the M layers being metal layers, or a quasi-metal such as TiN, the O layers being oxide layers containing ions, and the I layer being an ionic dielectric. The regions having a contoured surface may be formed of porous anodized alumina.

Abstract: A substrate that includes a base layer having a first principal surface defining a plurality of first trenches and intervening first lands, and a cover layer provided over the first principal surface of the base layer and covering the first trenches and first lands substantially conformally, wherein the surface of the cover layer remote from the first principal surface of the base layer comprises a plurality of second trenches and intervening second lands defined at a smaller scale than the first trenches and first lands. The substrate may be used to fabricate a capacitive element in which thin film layers are provided and conformally cover the second trenches and second lands of the cover layer, to create a metal-insulator-metal structure having high capacitance density.

Abstract: A semi-conductor structure with a crack-blocking three-dimensional structure is described. The semiconductor structure includes a substrate; a functional circuit structure disposed in an area of the substrate; and a three-dimensional structure having at least one continuous trench that extends perpendicularly towards a base surface of the substrate and that surrounds the area of the substrate containing the functional circuit structure.

Abstract: A capacitor structure that includes a silicon substrate having a trench structure formed therein; a dielectric disposed over a surface of the trench structure, conformal to the surface of the trench structure; and a filling layer disposed over the dielectric layer and into the trench structure, the filling layer including a conductive layer and a polymer layer.