Abstract: A method detects multipath propagation in a modulated digital signal. The method provides a first value of channel frequency, representing the modulated digital signal free of multipath propagation, providing a second value of said channel frequency, representing the modulated digital signal with multipath propagation, and comparing the first and second values. A method detects adjacent channel interference in a modulated digital signal by comparing first and second values of a characteristic parameter of the digital signal, respectively representing the digital signal free of adjacent channel interference and the digital signal affected by adjacent channel interference.

Abstract: The present invention relates to a high-speed interface for radio systems, in particular to a synchronous serial digital interface for a car radio. In an embodiment, the synchronous serial digital interface for at least dual radio receiver systems includes a master device and a slave device. The dual radio receiver system has an intermediate frequency. The master device and the slave device exchange data in a bi-directional manner on at least one communication channel; the master device and the slave device have a unique bit clock; the master device supplies a synchronization signal to the slave device. The synchronization signal has a frequency spectrum with an amplitude at the intermediate frequency lower than the amplitudes at the other frequencies of the synchronization signal.

Abstract: A method detects multipath propagation in a modulated digital signal. The method provides a first value of channel frequency, representing the modulated digital signal free of multipath propagation, providing a second value of said channel frequency, representing the modulated digital signal with multipath propagation, and comparing the first and second values. A method detects adjacent channel interference in a modulated digital signal by comparing first and second values of a characteristic parameter of the digital signal, respectively representing the digital signal free of adjacent channel interference and the digital signal affected by adjacent channel interference.

Abstract: A method for the determination of a bias current of a quartz oscillator that includes the phases of: defining a series of bias currents of prefixed values; supplying to said quartz oscillator a bias current value not yet used; verifying the presence of an oscillation signal at the output of said quartz oscillator; supplying in the negative case to said quartz oscillator a bias current value not yet used and repeating the preceding phase; verifying the presence of the correct oscillation frequency; supplying in the negative case a bias current not yet used to said quartz oscillator and repeating the phase of verifying the presence of an oscillation signal at the output of said quartz oscillator; storing, in the positive case, that the supplied current is valid; repeating the preceding phases up to the exhaustion of said series of values of bias currents; fixing as a bias current of said quartz oscillator the algebraic average of the currents regarded as valid.

Abstract: A method for the determination of a bias current of a quartz oscillator that includes the phases of: defining a series of bias currents of prefixed values; supplying to said quartz oscillator a bias current value not yet used; verifying the presence of an oscillation signal at the output of said quartz oscillator; supplying in the negative case to said quartz oscillator a bias current value not yet used and repeating the preceding phase; verifying the presence of the correct oscillation frequency; supplying in the negative case a bias current not yet used to said quartz oscillator and repeating the phase of verifying the presence of an oscillation signal at the output of said quartz oscillator; storing, in the positive case, that the supplied current is valid; repeating the preceding phases up to the exhaustion of said series of values of bias currents; fixing as a bias current of said quartz oscillator the algebraic average of the currents regarded as valid.

Abstract: The present invention relates to a high-speed interface for radio systems, in particular to a synchronous serial digital interface for car radio. In an its embodiment the synchronous serial digital interface for at least dual radio receiver systems comprises a master device and a slave device; the dual radio receiver systems having an intermediate frequency; the master device and the slave device exchange data in bi-directional manner on at least one communication channel; the master device and the slave device have a unique bit clock; the master device supply a synchronization signal to the slave device the synchronization signal has a frequency spectrum with an amplitude at the intermediate frequency lower than the amplitude of other frequencies.

Abstract: An interface for translating data of different voltages includes an input terminal structured to accept an input from a circuit supplied by a power supply having a first voltage level, as well as an output terminal structured to provide an output from the interface a first circuit portion powered by a power supply having the first voltage level, a second circuit portion is powered by a power supply having a second voltage level, and a power supply detection circuit structured to accept a detection signal and to maintain a correct output at the output terminal even after the power supply having the first voltage level no longer supplies the first voltage level to the interface.

Abstract: An interface for translating data of different voltages includes an input terminal structured to accept an input from a circuit supplied by a power supply having a first voltage level, as well as an output terminal structured to provide an output from the interface a first circuit portion powered by a power supply having the first voltage level, a second circuit portion is powered by a power supply having a second voltage level, and a power supply detection circuit structured to accept a detection signal and to maintain a correct output at the output terminal even after the power supply having the first voltage level no longer supplies the first voltage level to the interface.

Abstract: An output buffer circuit including an input node, an output stage, an output node that is connected to the output stage, and a control circuit that controls voltage variations during the rising and falling edges of the output signal. The control circuit compares the levels of the input signal and the output signal and drives the output stage. In a preferred embodiment, the control circuit includes first and second logic circuits that are each connected to the input and output nodes. The first logic circuit selectively enables operation of a first driving circuit, and the second logic circuit selectively enables operation of a second driving circuit. Additionally, a method for slew rate control during rising and falling edges of an output signal of an output buffer circuit is provided. According to the method, the level of the output signal and the level of the input signal are compared. If the input and output signals have different levels, a current is injected into or taken from the output node.

Abstract: A low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries, which comprises a master section and a slave section, is disclosed and claimed. The master section includes a master latch structure, a master coupling circuit which connects the master latch structure to one of two supply voltages, and an input coupling circuit for applying data to the flip-flop. The slave section includes a slave latch structure directly interposed between two supply voltages, and a slave coupling circuit which connects the slave latch structure to the master latch structure. The number of transistors required to realize the D flip-flop circuit implementation of the invention is minimized by enlarging the source areas of transistors in the input coupling circuit, which results in a large stray capacitance and insures optimum operation of the master latch. In addition, transistors in the slave latch structure have non-minimal gate lengths.

Abstract: A one-pin integrated crystal oscillator in a Colpitts configuration employs a differential amplifier, provided with a feedback network, as an input gain stage. This achieves an enhanced stability and independence from temperature variation, a high Q figure, and a short start-up with a relatively small area of integration.