Abstract: Device for cleaning teeth which comprises a dental floss fork provided with a grippable handle and with two rods with free ends spaced from each other and a dental floss, which is mounted with a bridge section between the free ends of the two rods of the dental floss fork. The dental floss has annular extension and the dental floss fork is provided with a guide, in which the dental floss is housed, for supporting it along its annular extension. The dental floss is slidably mounted within the guide.

Abstract: A communication device (10) comprises a conductor (11), a transceiver (12) coupled to the conductor (11) and a data processing unit (13) that is coupled to the transceiver (12). The communication device (10) is configured to determine a strength signal (ST) depending on a receiver signal (SR) received via the conductor (11) and to determine a proximity signal (SP) depending on a proximity of a body to the communication device (10). The data processing unit (13) is configured to generate a disable signal (STO) depending on at least a value of the strength signal (ST) and on at least a value of the proximity signal (SP).

Abstract: Device for cleaning teeth which comprises a dental floss fork (2) provided with a grippable handle (3) and with two rods (4) with free ends (4?) spaced from each other and a dental floss (5), which is mounted with a bridge section (5?) between the free ends (4?) of the two rods (4) of the dental floss fork (2). The dental floss (5) has annular extension and the dental floss fork (2) is provided with guide means (6), in which the dental floss (5) is housed, for supporting it along its annular extension. The dental floss (5) is slidably mounted within the guide means (6).

Abstract: A communication device (10) comprises a conductor (11), a transceiver (12) coupled to the conductor (11) and a data processing unit (13) that is coupled to the transceiver (12). The communication device (10) is configured to determine a strength signal (ST) depending on a receiver signal (SR) received via the conductor (11) and to determine a proximity signal (SP) depending on a proximity of a body to the communication device (10). The data processing unit (13) is configured to generate a disable signal (STO) depending on at least a value of the strength signal (ST) and on at least a value of the proximity signal (SP).

Abstract: A transceiver circuit with a front-end and a back-end is provided. The front-end has terminals for coupling to a first and a second capacitor and tunable resistors coupled between the terminals and a reference terminal. The front-end is configured to receive receiver signals at the terminals utilizing a first setting for the resistors. The front-end is configured to generate a receiver data packet based on the receiver signals. The back-end is configured to check the receiver data packet for errors with respect to a defined tuning data packet. If an error is found, the back-end sets the resistors to a default setting. If no errors are found, the back-end sets the resistors to a second setting.

Abstract: A connector for capacitive coupling of a first communicator and a second communicator of a communication system has a first, a second, a third and a fourth electrode, all of which are electrically conductive. The first and third electrodes are designed to be coupled to the first communicator. The second and fourth electrodes are designed to be coupled to the second communicator. The electrodes are designed to constitute capacitive couplings. Additionally, the first and the second electrode are designed to induce an attractive force between themselves by using a magnetic interaction. Analogously, the third and the fourth electrode are designed to induce an attractive force between themselves by using a magnetic interaction.

Abstract: A transceiver circuit with a front-end and a back-end is provided. The front-end has terminals for coupling to a first and a second capacitor and tunable resistors coupled between the terminals and a reference terminal. The front-end is configured to receive receiver signals at the terminals utilizing a first setting for the resistors. The front-end is configured to generate a receiver data packet based on the receiver signals. The back-end is configured to check the receiver data packet for errors with respect to a defined tuning data packet. If an error is found, the back-end sets the resistors to a default setting. If no errors are found, the back-end sets the resistors to a second setting.

Abstract: One embodiment of an apparatus for generating a time stamp includes a clock input, an event signal input and a time stamp output. A DLL is connected to the clock input, with a plurality of delay elements inside the DLL. An output of each of the delay elements is connected to a data input on a latch. An event signal input is connected to an enable input on each of the latches. An output of each of the latches is connected to the time stamp output. The apparatus is adapted to produce a value on the time stamp output indicating a point at which the event signal input transitions between transitions on the clock input.

Abstract: Traditionally, time stamp circuits have been used for precise digital time measurements. The resolution of these types of circuits, though, was generally limited by clock speed. Here, an apparatus is provided that performs time stamp operations and is not generally limited by clock speed. This apparatus generally uses an interpolator, counter, lathing circuits, and a synchronizer. Typically, the interpolator provides a residue signal to the synchronizer, and the synchronizer can determines whether to add the interpolation signal to a counter state based at least in part on a comparison of an event signal and the residue signal.

Abstract: Various apparatuses and methods for synchronizing time stamps are disclosed herein. For example, some embodiments of the present invention provide apparatuses for synchronizing a coarse time stamp with a fine time stamp. Such apparatuses include an event signal input, a clock input, a coarse time stamp generator having an input connected to the clock input, and a fine time stamp generator having a first input connected to the clock input, a second input connected to the event signal input, and a synchronization signal output. The apparatuses also include a synchronizer having a first input connected to the clock input, a second input connected to the event signal input, a third input connected to the synchronization signal output and an output connected to the coarse time stamp generator. The synchronizer is adapted to synchronize the coarse time stamp generator to the fine time stamp generator based at least in part on the synchronization signal output.

Abstract: One embodiment of an apparatus for generating a time stamp includes a clock input, an event signal input and a time stamp output. A DLL is connected to the clock input, with a plurality of delay elements inside the DLL. An output of each of the delay elements is connected to a data input on a latch. An event signal input is connected to an enable input on each of the latches. An output of each of the latches is connected to the time stamp output. The apparatus is adapted to produce a value on the time stamp output indicating a point at which the event signal input transitions between transitions on the clock input.

Abstract: A controller for an adjustable-frequency oscillator includes a first counter supplied with a stop-count value to count adjustable-frequency oscillator cycles divided by the ratio of desired frequency to reference oscillator frequency, to produce a stop signal when the first counter reaches the stop-count value. A second counter counts cycles of a reference oscillator starting from an initial number related to the stop-count value. The second counter stops counting and produces an end-count when the second counter receives the stop signal from the first counter. A resonant tank circuit includes a bank of capacitors with switches to select resonant tank circuit capacitors. The switches are selectively controlled using the end-count in the second counter. The stop-count value is set for the first counter so that the end count number in the second counter using a ones-complement binary format can be used to iteratively set the switches with minimal digital computation.

Abstract: A controller for an adjustable-frequency oscillator includes a first counter supplied with a stop-count value to count adjustable-frequency oscillator cycles divided by the ratio of desired frequency to reference oscillator frequency, to produce a stop signal when the first counter reaches the stop-count value. A second counter counts cycles of a reference oscillator starting from an initial number related to the stop-count value. The second counter stops counting and produces an end-count when the second counter receives the stop signal from the first counter. A resonant tank circuit includes a bank of capacitors with switches to select resonant tank circuit capacitors. The switches are selectively controlled using the end-count in the second counter. The stop-count value is set for the first counter so that the end count number in the second counter using a ones-complement binary format can be used to iteratively set the switches with minimal digital computation.

Abstract: A digital sigma-delta modulator requiring minimal die area and dissipating minimal power is formed with a plurality of integration stages coupled in tandem between an input node and an output node. The bit width of signals in the integration stages is progressively reduced from the first to the last integration stage without compromising modulator accuracy. A quantizer between the last integration stage and the output node provides the final reduction of signal bit width. The gain of the modulator feedforward and feedback paths are integer powers of two to further simplify the digital computation. In an exemplary implementation, three integration stages to form a third-order modulator are coupled in tandem between the input node and the output node. The gains of feedback and feedforward paths in one preferred embodiment are unity, and in some embodiments, one feedforward path has gain of 0.5.

Abstract: A variable word length data memory. The data memory disclosed has standard 16-bit word memory operation. The variable word length enables increased software efficiency in implementing software buffers using single memory locations parallel to the memory words as tags. Low-cost, efficient logic processing is enabled through a flag processor instruction set. This instruction set provides direct reference to flag memory, status test flags, and latched condition states.

Abstract: This application describes a method of multiplying numbers represented in multiple-word chains. The multiplication scheme allows for the multiplication of both signed and unsigned numbers of varying lengths. The multiplier block 30 executes a 17-bit by 17-bit two's complement multiply and multiply-accumulate in a single instruction cycle. A 4-bit shift value register with a 4 to 16 bit decoder 35 allows the multiplier to do a 1-16 bit barrel shift on either a 16-bit operand or an (N×16)-bit chain operand.

Abstract: Specialized microprocessor hardware 10 and a specialized instruction set that provides efficient data processing operations on long word length or bit length data. Instructions that manipulate data include a reserved bit-switch (in the form of a two bit field) whose status (A0) causes the instruction to be executed once to operate on a single word of data, or whose status (A0S) causes the instruction to be repeatedly executed as the instruction operates on a chain or list of sequential data, for example a data chain including N 16-bit words of data, wherein N is an integer. Every instruction word that manipulates data has a reserved bit switch that will cause the instruction to be executed either once operating on single word data or as a repeated execution of the same instruction operating on a chain or list of sequential data (n words).

Abstract: A variable word length data memory. The data memory disclosed has standard 16-bit word memory operation. The variable word length enables increased software efficiency in implementing software buffers using single memory locations parallel to the memory words as tags. Low-cost, efficient logic processing is enabled through a flag processor instruction set. This instruction set provides direct reference to flag memory, status test flags, and latched condition states.

Abstract: A variable word length data memory. The data memory disclosed has standard 16-bit word memory operation. The variable word length enables increased software efficiency in implementing software buffers using single memory locations parallel to the memory words as tags. Low-cost, efficient logic processing is enabled through a flag processor instruction set. This instruction set provides direct reference to flag memory, status test flags, and latched condition states.

Abstract: This application describes a method of protecting data and program code stored in an EPROM array from piracy. The security scheme allows for segmentation of the array to protect one section of the array from reading while programming a non-secure section. The security scheme also allows for protection of the entire array after programming is complete. It also incorporates a device to prevent tampering with the segmentation registers and a means to prevent circumvention of the security scheme even when the processor is in one or more of its test modes.