Patents by Inventor Francesco CLERICI

Francesco CLERICI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11906995
    Abstract: A voltage regulator coupled between a first node and second node includes a first (full-power) regulator circuit and a second (low-power) regulator circuit. In a first mode: the first regulator circuit is activated (with the second regulator circuit inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is kept de-activated when the voltage at the first node is a ground voltage. In a second mode: the first regulator circuitry in is active (with the second regulator circuitry inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is inactive when the voltage at the first node is a ground voltage. In a third mode: the second regulator circuitry is active (with the first regulator circuitry inactive) irrespective of the voltage at the first node being at the battery voltage or the ground voltage.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: February 20, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Daniele Mangano, Francesco Clerici, Pasquale Butta'
  • Patent number: 11906994
    Abstract: A voltage regulator is embedded in a circuit intermediate a first node (coupled to a battery) and a second node (supplying power to an external memory). The voltage regulator is activatable in a first mode of operation for startup during which an voltage is applied to the second node that increases towards a supply threshold. In response to the voltage at the second node reaching the supply threshold, the voltage regulator transitions to a second mode of operation where a programmable regulated voltage (higher than the supply threshold) is applied to the second node. In response to receipt of a low-power operation request, a first high-drive regulator circuitry is deactivated and a second low-power regulator circuitry is activated to provide a third mode of operation at low power.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: February 20, 2024
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS
    Inventors: Daniele Mangano, Andrei Tudose, Francesco Clerici, Pasquale Butta'
  • Publication number: 20220397923
    Abstract: A voltage regulator is embedded in a circuit intermediate a first node (coupled to a battery) and a second node (supplying power to an external memory). The voltage regulator is activatable in a first mode of operation for startup during which an voltage is applied to the second node that increases towards a supply threshold. In response to the voltage at the second node reaching the supply threshold, the voltage regulator transitions to a second mode of operation where a programmable regulated voltage (higher than the supply threshold) is applied to the second node. In response to receipt of a low-power operation request, a first high-drive regulator circuitry is deactivated and a second low-power regulator circuitry is activated to provide a third mode of operation at low power.
    Type: Application
    Filed: June 9, 2022
    Publication date: December 15, 2022
    Applicants: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS
    Inventors: Daniele MANGANO, Andrei TUDOSE, Francesco CLERICI, Pasquale BUTTA'
  • Publication number: 20220397924
    Abstract: A voltage regulator coupled between a first node and second node includes a first (full-power) regulator circuit and a second (low-power) regulator circuit. In a first mode: the first regulator circuit is activated (with the second regulator circuit inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is kept de-activated when the voltage at the first node is a ground voltage. In a second mode: the first regulator circuitry in is active (with the second regulator circuitry inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is inactive when the voltage at the first node is a ground voltage. In a third mode: the second regulator circuitry is active (with the first regulator circuitry inactive) irrespective of the voltage at the first node being at the battery voltage or the ground voltage.
    Type: Application
    Filed: June 9, 2022
    Publication date: December 15, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Daniele MANGANO, Francesco CLERICI, Pasquale BUTTA'
  • Patent number: 10135399
    Abstract: A common-mode feedback circuit includes a transconductor input stage with differential input terminals, and a frequency-compensated gain stage coupled to the transconductor input stage with differential output terminals. The common-mode feedback circuit also includes a feedback loop having a comparator configured to produce a feedback error signal for the transconductor input stage by comparing with a reference a common-mode sensing signal indicative of a common-mode voltage level sensed at the differential output terminals. In addition, the common-mode feedback loop includes a converter for converting the common-mode voltage level sensed at said differential output terminals into a current signal coupled to the comparator.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: November 20, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Francesco Carrara, Felice Alberto Torrisi, Francesco Clerici
  • Publication number: 20170163222
    Abstract: A common-mode feedback circuit includes a transconductor input stage with differential input terminals, and a frequency-compensated gain stage coupled to the transconductor input stage with differential output terminals. The common-mode feedback circuit also includes a feedback loop having a comparator configured to produce a feedback error signal for the transconductor input stage by comparing with a reference a common-mode sensing signal indicative of a common-mode voltage level sensed at the differential output terminals. In addition, the common-mode feedback loop includes a converter for converting the common-mode voltage level sensed at said differential output terminals into a current signal coupled to the comparator.
    Type: Application
    Filed: February 24, 2017
    Publication date: June 8, 2017
    Inventors: Francesco Carrara, Felice Alberto Torrisi, Francesco Clerici
  • Patent number: 9628028
    Abstract: A common-mode feedback circuit includes a transconductor input stage with differential input terminals, and a frequency-compensated gain stage coupled to the transconductor input stage with differential output terminals. The common-mode feedback circuit also includes a feedback loop having a comparator configured to produce a feedback error signal for the transconductor input stage by comparing with a reference a common-mode sensing signal indicative of a common-mode voltage level sensed at the differential output terminals. In addition, the common-mode feedback loop includes a converter for converting the common-mode voltage level sensed at said differential output terminals into a current signal coupled to the comparator.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: April 18, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Francesco Carrara, Felice Alberto Torrisi, Francesco Clerici
  • Publication number: 20160072448
    Abstract: A common-mode feedback circuit includes a transconductor input stage with differential input terminals, and a frequency-compensated gain stage coupled to the transconductor input stage with differential output terminals. The common-mode feedback circuit also includes a feedback loop having a comparator configured to produce a feedback error signal for the transconductor input stage by comparing with a reference a common-mode sensing signal indicative of a common-mode voltage level sensed at the differential output terminals. In addition, the common-mode feedback loop includes a converter for converting the common-mode voltage level sensed at said differential output terminals into a current signal coupled to the comparator.
    Type: Application
    Filed: June 22, 2015
    Publication date: March 10, 2016
    Inventors: Francesco CARRARA, Felice Alberto TORRISI, Francesco CLERICI