Patents by Inventor Francesco Mastroianni
Francesco Mastroianni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071483Abstract: Disclosed are techniques for correcting drift accumulation in memory cells. In some aspects, the techniques described herein relate to a memory device including: a memory array, the memory array including a set of memory cells; and a memory controller configured to read data from the memory array, the memory controller configured to: sense a first distribution of the set of memory cells, detect a missing cell in the first distribution, increase a voltage on the missing cell causing the missing cell to be read as part of the first distribution, detect that a second memory cell in a second distribution was read while sensing the first distribution, and mask the second memory cell and mark the second memory cell as belonging to the second distribution.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Inventors: Christophe Vincent Antoine Laurent, Francesco Mastroianni, Andrea Martinelli, Efrem Bolandrina, Lucia Di Martino, Riccardo Muzzetto, Zhongyuan Lu, Karthik Sarpatwari, Nevil N. Gajera
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Publication number: 20240038301Abstract: Methods, systems, and devices for memory cell read operation techniques are described. A memory device may determine a starting voltage for a second phase of a read operation for a set of memory cells which may have a different magnitude than a magnitude of a starting voltage of a first phase of the read operation. For example, the memory device may use an ending voltage of the first phase to determine the starting voltage for the second phase. In some cases, the starting voltage for the second phase may correspond to a difference of a voltage offset and the ending voltage of the first phase. As part of the second phase of the read operation, the memory device may apply a sequence of voltages to the set of memory cells in accordance with the determined starting voltage of the second phase.Type: ApplicationFiled: July 29, 2022Publication date: February 1, 2024Inventors: Riccardo Muzzetto, Francesco Mastroianni, Ferdinando Bedeschi, Nevil N. Gajera
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Patent number: 11618491Abstract: A dolly for indoor and outdoor use including a supporting frame extending along a main axis of extension and a loading platform mounted above said frame. The dolly also includes at least one steering and drive wheel coupled to the bottom of the frame and at least one pair of idle wheels coupled to the bottom of the frame and positioned symmetrically relative to the main axis of extension. The dolly also includes a control structure including a plurality of sensors configured for measuring a plurality of operating parameters of the dolly and for generating respective signals representing operating parameters and a processing unit configured to receive the representative signals and to impart a steering command to the at least one steering and drive wheel at least as a function of the representative signals.Type: GrantFiled: May 4, 2021Date of Patent: April 4, 2023Assignee: TOYOTA MATERIAL HANDLING MANUFACTURING ITALY S.P.AInventor: Francesco Mastroianni
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Publication number: 20220199137Abstract: Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.Type: ApplicationFiled: December 28, 2021Publication date: June 23, 2022Inventors: Andrea Martinelli, Francesco Mastroianni, Kiyoshi Nakai
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Patent number: 11217291Abstract: Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.Type: GrantFiled: July 11, 2019Date of Patent: January 4, 2022Assignee: Micron Technology, Inc.Inventors: Andrea Martinelli, Francesco Mastroianni, Kiyoshi Nakai
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Publication number: 20210347398Abstract: A dolly for indoor and outdoor use including a supporting frame extending along a main axis of extension and a loading platform mounted above said frame. The dolly also includes at least one steering and drive wheel coupled to the bottom of the frame and at least one pair of idle wheels coupled to the bottom of the frame and positioned symmetrically relative to the main axis of extension. The dolly also comprises includes a control structure including a plurality of sensors configured for measuring a plurality of operating parameters of the dolly and for generating respective signals representing operating parameters and a processing unit configured to receive the representative signals and to impart a steering command to the at least one steering and drive wheel at least as a function of the representative signals.Type: ApplicationFiled: May 4, 2021Publication date: November 11, 2021Inventor: Francesco MASTROIANNI
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Publication number: 20210012825Abstract: Methods, systems, and devices for circuitry borrowing in memory arrays are described. In one example, a host device may transmit an access command associated with data for a first memory section to a memory device. The first memory section may be located between a second memory section and a third memory section. A first set of circuitry shared by the first memory section and the second memory section may be operated using drivers associated with the first memory section and drivers associated with the second memory section. A second set of circuitry shared by the first memory section and the third memory section may be operated using drivers associated with the first memory section and drivers associated with the third memory section. An access operation may be performed based on operating the first set of circuitry and the second set of circuitry.Type: ApplicationFiled: July 11, 2019Publication date: January 14, 2021Inventors: Andrea Martinelli, Francesco Mastroianni, Kiyoshi Nakai
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Patent number: 9558799Abstract: A memory device includes an operation having a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row address to select data for a row data buffer, and a phase to output the data from the row data buffer, wherein an activate command starts and following activate commands are ignored until a preset time has elapsed.Type: GrantFiled: November 30, 2015Date of Patent: January 31, 2017Assignee: Micron Technology, Inc.Inventors: Marco Ferrario, Christophe Vincent Antoine Laurent, Francesco Mastroianni
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Patent number: 9405475Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.Type: GrantFiled: November 6, 2014Date of Patent: August 2, 2016Assignee: Micron Technology, Inc.Inventors: Giulio Albini, Emanuele Confalonieri, Francesco Mastroianni
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Publication number: 20160086662Abstract: A memory device includes an operation having a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row address to select data for a row data buffer, and a phase to output the data from the row data buffer, wherein an activate command starts and following activate commands are ignored until a preset time has elapsed.Type: ApplicationFiled: November 30, 2015Publication date: March 24, 2016Inventors: Marco Ferrario, Christophe Vincent Antoine Laurent, Francesco Mastroianni
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Patent number: 9208835Abstract: A phase-change memory includes a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row address to select data for a row data buffer, and a phase to output the data from the row data buffer, where an activate command starts and following activate commands are ignored until a preset time has elapsed.Type: GrantFiled: December 29, 2009Date of Patent: December 8, 2015Assignee: Micron Technology, Inc.Inventors: Marco Ferrario, Christophe Vincent Antoine Laurent, Francesco Mastroianni
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Publication number: 20150067254Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.Type: ApplicationFiled: November 6, 2014Publication date: March 5, 2015Inventors: Giuliu Albini, Emanuele Confalonieri, Francesco Mastroianni
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Patent number: 8918594Abstract: Apparatus and methods disclose techniques to control access to a memory array. The memory array can be accessed by either a first interface or a second interface. A switch register grants privilege levels, which control access. For example, a high privilege level can grant access and a low privilege level can deny access. A status register indicates when an interface with a high privilege level is busy accessing the memory array.Type: GrantFiled: November 16, 2010Date of Patent: December 23, 2014Assignee: Micron Technology, Inc.Inventors: Giulio Albini, Emanuele Confalonieri, Francesco Mastroianni
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Publication number: 20130077393Abstract: A Phase-Change Memory (PCM) that allows an Activate command to start and all following Activate commands are ignored until a time tRC has elapsed.Type: ApplicationFiled: December 29, 2009Publication date: March 28, 2013Inventors: Marco Ferrario, Christophe Vincent Antoine Laurent, Francesco Mastroianni
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Publication number: 20120124313Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.Type: ApplicationFiled: November 16, 2010Publication date: May 17, 2012Applicant: Micron Technology, Inc.Inventors: Giulio Albini, Emanuele Confalonieri, Francesco Mastroianni
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Patent number: 7761675Abstract: A non-volatile memory device of flash type includes first memory cells for storing data, second memory cells for storing protection information of the first memory cells, and a circuit for updating the protection information that includes a circuit for writing a plurality of versions of the protection information in the second memory cells, and a circuit for identifying a current version of the protection information.Type: GrantFiled: May 10, 2006Date of Patent: July 20, 2010Inventors: Francesco Mastroianni, Antonino Mondello, Elena Cussotto, Massimiliano Mollichelli, Mauro Sali
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Publication number: 20070016735Abstract: A non-volatile memory device of flash type includes first memory cells for storing data, second memory cells for storing protection information of the first memory cells, and a circuit for updating the protection information that includes a circuit for writing a plurality of versions of the protection information in the second memory cells, and a circuit for identifying a current version of the protection information.Type: ApplicationFiled: May 10, 2006Publication date: January 18, 2007Applicant: STMicroelectronics S.r.I.Inventors: Francesco Mastroianni, Antonino Mondello, Elena Cussotto, Massimiliano Mollichelli, Mauro Sali
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Patent number: 6940756Abstract: A non-volatile memory device suitable to be programmed in a sequential mode. The device includes a plurality of blocks of memory cells each one for storing a word, each block being identified by an address. An input circuit for loading an input address at the beginning of a programming procedure and an internal circuit for setting an internal address to the input address. The device further includes a data input circuit for loading a predetermined number of input words in succession, and a latch circuit for latching a page consisting of the predetermined number of input words. The memory then executes a programming operation including writing the page in the blocks identified by consecutive addresses starting from the internal address, and increments the internal address of the predetermined number in response to the completion of the programming operation.Type: GrantFiled: December 18, 2003Date of Patent: September 6, 2005Assignee: STMicroelectronics S.r.l.Inventors: Francesco Mastroianni, Massimiliano Scotti, Antonio Geraci, Andrea Pozzato
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Publication number: 20040165434Abstract: A non-volatile memory device suitable to be programmed in a sequential mode. The device includes a plurality of blocks of memory cells each one for storing a word, each block being identified by an address. An input circuit for loading an input address at the beginning of a programming procedure and an internal circuit for setting an internal address to the input address. The device further includes a data input circuit for loading a predetermined number of input words in succession, and a latch circuit for latching a page consisting of the predetermined number of input words. The memory then executes a programming operation including writing the page in the blocks identified by consecutive addresses starting from the internal address, and increments the internal address of the predetermined number in response to the completion of the programming operation.Type: ApplicationFiled: December 18, 2003Publication date: August 26, 2004Applicant: STMicroelectronics S.r.I.Inventors: Francesco Mastroianni, Massimiliano Scotti, Antonio Geraci, Andrea Pozzato
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Publication number: 20040136218Abstract: The memory device includes a plurality of memory chips of a certain capacity assembled in a single package and sharing input/output pins, the memories being selectable and singularly enabled one at the time by appropriate external commands coherently with the currently addressed memory location. The device uses only one external enable/disable logic command applied through a single dedicated pin. Each of the memory chips has a number of additional input/output pads equal to 2*n, where 2n is the number of memory chips contained in the device, and a dedicated circuit that generates an internal enable/disable command, as a function of logic inputs corresponding to the logic states of the additional pads and the external enable/disable command.Type: ApplicationFiled: December 3, 2003Publication date: July 15, 2004Applicant: STMicroelectronics S.r.l.Inventors: Alessandro Magnavacca, Andrea Bellini, Francesco Mastroianni, Marco Defendi