Patents by Inventor Francesco Rezzi
Francesco Rezzi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113530Abstract: The present invention relates to a device (200, 800) for active balancing of a battery (B), the battery (B) comprising a plurality of units (U1-UN) connected in series at a plurality of nodes (N1-NN?1), the device comprising at least one DC/DC converter (210, 610, 710, 8101-810N) configured to transfer charges between a first group (G1) of the plurality of units (U1-UN) and a second group (G2) of the plurality of units (U1-UN), at least one of the first group (G1) and second group (G2 comprising a plurality of the units (U1-UN).Type: ApplicationFiled: October 12, 2022Publication date: April 4, 2024Applicant: INVENTVM Semiconductor SRLInventors: Francesco REZZI, Domenico GRANOZIO, Luigi PINNA
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Patent number: 11799453Abstract: A circuit for driving a capacitive load includes an amplifier for driving the load based on an input signal, the amplifier comprising at least a boost converter, a dynamic model configured to track a capacitance of the load and a voltage of the source for powering at least parts of the circuit, an adaptive filter, configured to filter the input signal based on an output of the dynamic model.Type: GrantFiled: March 18, 2022Date of Patent: October 24, 2023Assignee: INVENTVM SEMICONDUCTOR SRLInventors: Francesco Rezzi, Darjn Esposito, Enrico Oberti, Michele Chiabrera, Marco Musacci
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Publication number: 20230299750Abstract: A circuit for driving a capacitive load includes an amplifier for driving the load based on an input signal, the amplifier comprising at least a boost converter, a dynamic model configured to track a capacitance of the load and a voltage of the source for powering at least parts of the circuit, an adaptive filter, configured to filter the input signal based on an output of the dynamic model.Type: ApplicationFiled: March 18, 2022Publication date: September 21, 2023Inventors: Francesco REZZI, Darjn ESPOSITO, Enrico OBERTI, Michele CHIABRERA, Marco MUSACCI
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Patent number: 10333525Abstract: An apparatus includes a temperature sensor, a digitally-controlled capacitor and a processor. The temperature sensor is coupled to a crystal oscillator and configured to generate an input signal depending on a temperature of the crystal oscillator. The digitally-controlled capacitor is connected to the crystal oscillator and configured to receive a control signal and, based on the control signal, to control a frequency of an output signal generated by the crystal oscillator. The processor is configured to receive the input signal from the temperature sensor, to convert the input signal into the control signal based on parameters that characterize the crystal oscillator and the digitally-controlled capacitor, and to apply the control signal to the digitally-controlled capacitor.Type: GrantFiled: December 6, 2016Date of Patent: June 25, 2019Assignee: MARVELL INTERNATIONAL LTD.Inventors: Gabriele Gandolfi, Giacomo Bernardi, Marco Bongiorni, Michele Chiabrera, Vittorio Colonna, Alberto Demarziani, Stefano Marchese, Alessio Pelle, Francesco Rezzi, Alessandro Savo
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Patent number: 9806682Abstract: Implementations of a class-D amplifier can be used to amplify an input analog signal and provide to a load a multilevel amplified signal having an amplitude larger than a voltage level of a power source used by the class-D amplifier.Type: GrantFiled: February 22, 2016Date of Patent: October 31, 2017Assignee: Marvell International Ltd.Inventors: Bruno Marcone, Francesco Rezzi
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Patent number: 9800217Abstract: Technologies are described to DC-couple an integrated amplifier system to a source that provides a signal with an unknown DC component, for example to DC-couple an integrated audio codec to an analog microphone. In one aspect, methods include receiving, by an amplifier, a signal having an unknown DC component, and issuing an amplified signal; low pass filtering, with respect to a cutoff frequency, by a feedback circuit coupled between an output of the amplifier and an input of the amplifier, the amplified signal issued at the output of the amplifier to generate a filtered signal having frequencies lower than the cutoff frequency; and injecting, by the feedback circuit, the filtered signal into the input of the amplifier to cancel the unknown DC component below the cutoff frequency.Type: GrantFiled: February 26, 2015Date of Patent: October 24, 2017Assignee: Marvell International Ltd.Inventors: Gabriele Gandolfi, Vittorio Colonna, Francesco Rezzi
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Patent number: 9048790Abstract: Aspects of the disclosure provide an audio amplification system. The audio amplification system includes an amplifier configured to amplify an audio signal, and a power supply module external to the amplifier that is configured to provide to the amplifier a supply voltage having a voltage level that is selected from at least two possible voltage levels based on an output volume level for the audio signal. In an example, the amplifier is a Class AB amplifier.Type: GrantFiled: April 14, 2011Date of Patent: June 2, 2015Assignee: Marvell International Ltd.Inventors: Asaf Refaeli, Francesco Rezzi, Giuseppe De Vita
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Patent number: 8779961Abstract: A system including a clock generator configured to generate a clock; a plurality of analog-to-digital converters each configured to convert a signal based on the clock, and to output a first number of bits in response to converting the signal based on the clock; and an averaging module configured to receive the first number of bits from each of the plurality of analog-to-digital converters, and to output a second number of bits. The second number of bits is greater than the first number of bits.Type: GrantFiled: November 1, 2012Date of Patent: July 15, 2014Assignee: Marvell World Trade Ltd.Inventors: Sehat Sutardja, Giovanni Antonio Cesura, Francesco Rezzi, Rinaldo Castello
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Patent number: 7888973Abstract: The present disclosure provides for a time to digital converter (TDC). The time to digital converter can include a reference ingress that receives a reference signal and passes the reference signal through multiple delay elements, a clock signal ingress that receives a clock signal and passes the clock signal through another set of delay elements, and multiple comparators, which are fewer in number than the total number of delay elements. The multiple comparators 1) receive the delayed reference and delayed clock signals and 2) output a set of comparison results for comparisons of pairs of delayed references and delayed clock signals.Type: GrantFiled: June 4, 2008Date of Patent: February 15, 2011Assignee: Marvell International Ltd.Inventors: Francesco Rezzi, Antonio Liscidini
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Patent number: 7880545Abstract: The present invention provides compensation for circuits. In one embodiment, a compensation circuit has a first terminal coupled to an output terminal of the circuit and a second terminal coupled to feed back the output voltage to an internal node. A damping circuit may also be coupled to the output terminal. The damping circuit adds a pole and a zero to the transfer function of the circuit. In one embodiment, the damping circuit modifies the effect of the output impedance of a load on the transfer function to increase the phase margin of the circuit such that the circuit remains stable over an increased range of output capacitor values.Type: GrantFiled: March 3, 2009Date of Patent: February 1, 2011Assignee: Marvell International Ltd.Inventors: Alessandro Venca, Daniele Ottini, Francesco Rezzi, Rinaldo Castello
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Patent number: 7705635Abstract: In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A source-follower circuit includes a current source and a source follower output, and the source follower output is coupled to the output node. A second MOS transistor selectively couples the source-follower circuit to a second reference voltage when the output node is to be in the second state.Type: GrantFiled: August 9, 2007Date of Patent: April 27, 2010Assignee: Marvell International Ltd.Inventors: Francesco Rezzi, Nicola Ghittori, Giovanni Antonio Cesura, Shafiq M. Jamal
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Patent number: 7629909Abstract: In a circuit to convert a voltage range of a control signal, a first switch selectively couples, based on the control signal, an output node to a first reference voltage when the output node is to be in a first state. A second switch selectively establishes, based on the control signal, a second reference voltage when the output node is to be in a second state, the second state being a logical complement of the first state. A feedback control loop is coupled to the output node to maintain the second reference voltage in response to voltage fluctuation at the output node. The feedback control loop includes a current mirror and a transistor coupled to the current mirror. The transistor is controlled by feedback from the output node to modify a biasing current established by the current mirror to thereby counteract the voltage fluctuation.Type: GrantFiled: August 9, 2007Date of Patent: December 8, 2009Assignee: Marvell International Ltd.Inventors: Francesco Rezzi, Nicola Ghittori, Giovanni Antonio Cesura, Shafiq M. Jamal
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Patent number: 7609186Abstract: In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second transistor selectively discharges the output node toward a second reference voltage via a resistor when the output node is to transition from the first state to a second state, the second state being a logical complement of the first state. A source-follower circuit has a source follower output coupled to the output node and has a dynamic current source, the dynamic current source having a control input coupled to the resistor. A third transistor selectively couples the source follower output to the dynamic current source when the output node is to be in the second state.Type: GrantFiled: August 9, 2007Date of Patent: October 27, 2009Assignee: Marvell International Ltd.Inventors: Francesco Rezzi, Nicola Ghittori, Giovanni Antonio Cesura, Shafiq M. Jamal
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Patent number: 7605608Abstract: In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second MOS transistor selectively discharges the output node toward a second reference voltage when the output node is to transition from the first state to a second state, the second state a logical complement of the first state. An output of a source-follower circuit, having a current source, is coupled to the output node. A third MOS transistor selectively couples the current source of the source-follower circuit to the second reference voltage when the output node is to be in the second state.Type: GrantFiled: August 9, 2007Date of Patent: October 20, 2009Assignee: Marvell International Ltd.Inventors: Francesco Rezzi, Nicola Ghittori, Giovanni Antonio Cesura, Shafiq M. Jamal
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Patent number: 7595745Abstract: In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a switch selectively couples an output node to a first reference voltage when the output node is to be in a first state based on the control signal. A source-follower circuit having a current source establishes a second reference voltage. A logic circuit coupled to the switch and the source-follower circuit and having a logic gate selectively discharges, in accordance with the control signal, the output node to the second reference voltage when the output node is to transition from the first state to a second state.Type: GrantFiled: August 9, 2007Date of Patent: September 29, 2009Assignee: Marvell International Ltd.Inventors: Francesco Rezzi, Nicola Ghittori, Giovanni Antonio Cesura, Shafiq M. Jamal
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Patent number: 7511649Abstract: In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A second MOS transistor has a source coupled to the output node and a gate coupled to a bias voltage. A current source circuit selectively biases the second MOS transistor to act as part of a source-follower circuit when the output node is to be in a second state. Additionally, a memory circuit has an input coupled to the output node, and an output. The memory circuit is configured to temporarily store a Boolean value of the output node when the output node transitions from the first state to the second state. Further, a discharging circuit is coupled to the output node and a second reference voltage.Type: GrantFiled: August 28, 2007Date of Patent: March 31, 2009Assignee: Marvell International Ltd.Inventors: Francesco Rezzi, Nicola Ghittori, Giovanni Antonio Cesura, Shafiq M. Jamal, Stefano Marchesi
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Patent number: 6662338Abstract: A Viterbi detector receives a signal that represents a sequence of values. The detector recovers the sequence from the signal by identifying surviving paths of potential sequence values and periodically eliminating the identified surviving paths having a predetermined parity. By recognizing the parity of portions of a data sequence, such a Viterbi detector more accurately recovers data from a read signal having a reduced SNR and thus allows an increase in the storage density of a disk drive's storage disk. Specifically, the Viterbi detector recovers only sequence portions having a recognized parity such as even parity and disregards sequence portions having unrecognized parities. If one encodes these sequence portions such that the disk stores them having the recognized parity, then an erroneously read word is more likely to have an unrecognized parity than it is to have the recognized parity.Type: GrantFiled: September 30, 1999Date of Patent: December 9, 2003Assignee: STMicroelectronics, Inc.Inventors: Francesco Rezzi, Marcus Marrow
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Patent number: 6654924Abstract: A system and method for algebraically correcting errors in complex digitized phase signals from a magneto-resistive or giant magneto-resistive (MR/GMR) head readback waveform includes a data state machine that encodes phase symbols into data bits in accordance with, e.g., the (1, 10) constraint and a parity state machine that generates parity symbols such that a single inserted parity symbol does not violate the (1, 7) constraint in a run length limited code and furthermore the data following the insertion will not violate the (1, 10) constraint in a run length limited code. The state machines can be used as a trellis to perform maximum likelihood decoding on received coded data, thus performing soft algebraic error detection on received data. The invention thus guarantees better overall error rate performance than hard decision post processing of blocks of detected bits by a parity check matrix which is otherwise vulnerable to loss of bit synchronization at high linear density recording.Type: GrantFiled: September 29, 2000Date of Patent: November 25, 2003Assignee: International Business Machines CorporationInventors: Martin Aureliano Hassner, Francesco Rezzi, Barry Marshall Trager
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Patent number: 6604204Abstract: A synchronizer circuit includes an input terminal, an output terminal, and a recovery circuit coupled to the input and output terminals. The input terminal receives an input signal that includes a sync mark, and the recovery circuit is operable to recover the sync mark from the input signal and to generate a synchronization signal on the output terminal in response to the recovered synchronization mark. For example, such a synchronizer circuit can recover the synchronization mark from a read signal and locate the beginning of a data stream for a Viterbi detector that is separate from the circuit. By performing the sync-recovery function in a separate circuit, one can reduce the complexity and increase the data-recovery speed of the Viterbi detector. Furthermore, the synchronizer circuit can recover the sync mark by executing state-transition routines in alignment with the input signal. For example, one can align the synchronizer circuit's state-transition routines to the preamble of the read signal.Type: GrantFiled: September 30, 1999Date of Patent: August 5, 2003Assignee: STMicroelectronics, Inc.Inventors: Hakan Ozdemir, Francesco Rezzi
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Patent number: 6587059Abstract: A code word includes a first group of data bits and includes code bits that represent a second group of data bits. One embodiment of the code word has a minimum probability of bit transitions among its bits. Another embodiment of the code word includes a parity bit. Unlike conventional codes, a code that includes such a code word can have both a high efficiency and small error propagation. Additionally, by including fewer bit transitions, a sequence of such code words causes less read noise, and thus causes fewer read errors as compared to sequences of known code words. Moreover, the code word can include a parity bit to allow improved error detection as compared to known error-detection techniques. Therefore, such a code word can significantly increase the effective write and read speeds of a disk drive.Type: GrantFiled: November 15, 2002Date of Patent: July 1, 2003Assignee: STMicroelectronics, Inc.Inventors: Francesco Rezzi, Marcus Marrow