Abstract: A work group computing system for facilitating programmable logic device design among multiple engineers has a global work space including design project source files, a compilation basis, a compilation report text file, a binary assignments database and a user-readable assignments text file. Any number of local work spaces contain downloaded versions of any of the project source files, local compilation processing results for that user and a local assignment database containing records of downloaded assignments. Downloaded project source files or assignments are assigned states by the user such as default, locked, owned-write, owned-read only to facilitate coordination amongst the user engineers. The system controls editing of files so that two engineers may not inadvertently edit the same global source file at the same time.

Abstract: A programmable logic device architecture with a highly routable programmable interconnect structure. The arrangement of the logic array blocks (LABs), programmable interconnect structure, and other logical elements forms a Clos network. After specific constraints have been met, the architecture is guaranteed to route. The architecture is provably routable when there is no fan-out in the middle stage. A LAB (A-200) comprises an input multiplexer region (A-504), logic elements (A-300), input-output pins (A-516), and output multiplexer region (A-508). Furthermore, a logic device and a method of operating a logic device. The device includes logic elements (B-240) that perform desired logic functions and routing functions. The logic elements (B-240) are arranged in larger logic blocks known as logic array blocks (B-230) that have local interconnection systems. The logic array blocks (B-230) are configured to provide global interconnections.

Abstract: A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region).

Abstract: A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface (“PCI”) signaling protocol. Regions of programmable logic within the device are closely coupled to the data signal output pins and clock signal input pins such that delay between application of a clock signal to the device and output of a data signal from the device is within PCI signal standards for delay. The device also includes output circuitry that can be configured to selectively invert signals to output enable and data input enable terminals of the output circuitry.

Abstract: A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region).

Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors, and each column has a plurality of adjacent vertical conductors. The regions in a row are interspersed with groups of local conductors which interconnect the adjacent regions and the associated horizontal and vertical conductors. The local conductors can also be used for intra-region communication, as well as communication between adjacent regions. Secondary signals such as clocks and clears for the regions can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by various techniques for sharing these memory cells.

Abstract: A method and mechanism for mapping heterogeneous logic elements in a portion of electronic design compilation for a programmable integrated circuit is disclosed. Specifically, the invention provides a method to perform the technology mapping of heterogeneous logic elements in a programmable logic device such as selectively choosing the best combination of product term logic elements and look up table logic elements.

Abstract: A logic device and a method of operating a logic device. The device includes logic elements (240) that perform desired logic functions and routing functions. The logic elements (240) are arranged in larger logic blocks known as logic array blocks (230) that have local interconnection systems. The logic array blocks (230) are configured to provide global interconnections. The configuration provides a Clos network, whereby a signal may be routed from any input to any output without blocking.

Abstract: The invention relates to an integrated circuit that can be configured to operate as a content addressable memory. The integrated circuit includes a first functional block that stores at least one keyword dataword which is associated with a group of associated data words. The integrated circuit also includes a second functional block that stores the group of associated datawords. The second functional block is connected to the first functional block in such a way that if a request dataword received at the first functional block matches at least one keyword dataword stored therein, then an associated result dataword included in the group of associated data words stored in the second functional block is output by the second functional block. Typically, the integrated circuit chip is a complex programmable logic device architecture (CPLD).

Abstract: A programmable logic array integrated circuit device includes regions of programmable logic, regions of memory, and a programmable network of interconnection conductors for selectively conveying signals to, from, and between the regions of logic and memory. The memory regions are usable as content addressable memory. Circuitry is provided for facilitating programming of the memory in content addressable mode.

Abstract: A technique is disclosed for performing an incremental recompile of an electronic design that has been previous compiled and then changed by a designer. This is accomplished by identifying a "sub-netlist" within the larger netlist of the changed design. The sub-netlist contains the sphere of influence of the designer's changes to the original design. During incremental recompile, only the sub-netlist is compiled; the remainder of the netlist is left as is from the previous compile. After the sub-netlist is synthesized, it is integrated back into the synthesized netlist from the previous compilation. The newly synthesized netlist for the changed design is mapped to logic cells which are then fit onto a target hardware device.

Abstract: A look-up-table-based programmable logic device is provided with memory circuitry which can be operated either as random access memory ("RAM") or to perform product term ("p-term") logic. Each individual row of the memory is separately addressable for writing data to the memory or, in RAM mode, for reading data from the memory. Alternatively, multiple rows of the memory are addressable in parallel to read p-terms from the memory. The memory circuitry of the invention is particularly useful as an addition to look-up-table-type programmable logic devices because the p-term capability of the memory circuitry provides an efficient way to perform wide fan-in logic functions which would otherwise require trees of multiple look-up tables.

Abstract: A technique for allowing local compilation at any level within a design hierarchy tree for a programmable logic device allows a user to compile within the context of the entire design using inherited parameter values and assignments from any parent nodes within the design hierarchy tree. A user is allowed to perform an isolated, local compilation that gives a compilation result as if the lower level node had been compiled within the context of the complete design. This local compilation is performed even though assignments, parameters, and logic options of parent nodes have not been compiled. An "action point" is specified at a node where a local compilation, timing analysis or simulation is to occur. A method compiles design source files that represent a PLD design. The design source files specify design entities that are represented as nodes in a design hierarchy tree. A first step analyzes the design source files to determine what design entities are represented in the source files.

Abstract: A look-up-table-based programmable logic device is provided with memory circuitry which can be operated either as random access memory ("RAM") or to perform product term ("p-term") logic. Each individual row of the memory is separately addressable for writing data to the memory or, in RAM mode, for reading data from the memory. Alternatively, multiple rows of the memory are addressable in parallel to read p-terms from the memory. The memory circuitry of the invention is particularly useful as an addition to look-up-table-type programmable logic devices because the p-term capability of the memory circuitry provides an efficient way to perform wide fan-in logic functions which would otherwise require trees of multiple look-up tables.

Abstract: A programmable logic device has subregions of programmable logic grouped together in logic regions. The subregions in each region share several control signals, which can be selected either from relatively global conductors on the device or from data inputs to the region. The control signals allow synchronous or asynchronous clearing of a register in each subregion. The control signals also allow synchronous loading of the register in each subregion, and the data loaded can be either one of the data inputs to the subregion (so-called lonely register operation) or a signal produced by the logic of the subregion.

Abstract: A programmable logic device has regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Horizontal interconnection conductors are associated with each row, and vertical interconnection conductors are associated with each column. Local conductors are interspersed between adjacent pairs of regions in each row for supplying signals to the regions on both sides of the local conductors. Subregions of programmable logic in each region generally have a local output and a global output. The global output is only usable to output to the relatively long-distance horizontal and vertical conductors. The local output is additionally usable as a local feedback and as a local connection to an adjacent region.

Abstract: A work group computing system for facilitating programmable logic device design among multiple engineers has a global work space including design project source files, a compilation basis, a compilation report text file, a binary assignments database and a user-readable assignments text file. Any number of local work spaces contain downloaded versions of any of the project source files, local compilation processing results for that user and a local assignment database containing records of downloaded assignments. Downloaded project source files or assignments are assigned states by the user such as default, locked, owned-write, owned-read only to facilitate coordination amongst the user engineers. The system controls editing of files so that two engineers may not inadvertently edit the same global source file at the same time.

Abstract: A programmable logic array integrated circuit device has a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of regions. The output signals of several regions share a group of drivers for applying region output signals to interconnection conductors that convey signals between regions. This conserves driver resources and increases signal routing flexibility. Various approaches can be used for configuring the interconnection conductors to also conserve interconnection conductor resources. Logic regions may be used to directly drive specific input/output cells, thereby simplifying signal routing to the I/O cells and also possibly simplifying the structure of the I/O cells (e.g., by allowing certain I/O cell functions to be performed in the associated logic region).

Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors, and each column has a plurality of adjacent vertical conductors. The regions in a row are interspersed with groups of local conductors which interconnect the adjacent regions and the associated horizontal and vertical conductors. The local conductors can also be used for intra-region communication, as well as communication between adjacent regions. Secondary signals such as clocks and clears for the regions can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by various techniques for sharing these memory cells.

Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of interesting rows and columns. Interconnection conductors are associated with each row and column. The interconnection conductors associated with each row include some that extend continuously along the entire length of the row and some that extend continuously along only the left or right half of the row. To increase the flexibility with which the logic regions can be connected to the row and column conductors, adjacent regions are paired and circuitry is provided for allowing the outputs of each pair to be swapped for driving the row and column conductors. Registers in logic regions can still be used for other purposes when not being used to register the main combinatorial outputs of the logic regions. Many other enhanced features are also provided.