Patents by Inventor Francis Gabriel Celii
Francis Gabriel Celii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8093070Abstract: A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.Type: GrantFiled: February 15, 2007Date of Patent: January 10, 2012Assignee: Texas Instruments IncorporatedInventors: Francis Gabriel Celii, Kezhakkedath R. Udayakumar, Gregory B. Shinn, Theodore S. Moise, Scott R. Summerfelt
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Patent number: 7985603Abstract: A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.Type: GrantFiled: February 4, 2008Date of Patent: July 26, 2011Assignee: Texas Instruments IncorporatedInventors: Francis Gabriel Celii, Robert Kraft, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Theodore S. Moise
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Patent number: 7811882Abstract: A method of manufacturing a semiconductor device. The method comprises fabricating a ferroelectric capacitor. The capacitor's fabrication includes forming conductive and ferroelectric material layers on a semiconductor substrate, forming a hardmask layer on the conductive and ferroelectric material layers, forming an organic bottom antireflective coating layer on the hardmask layer, and, patterning the organic bottom antireflective coating layer. Seasoning in a hardmask etching chamber is substantially unaffected by the patterning.Type: GrantFiled: January 13, 2009Date of Patent: October 12, 2010Assignee: Texas Instruments IncorporatedInventor: Francis Gabriel Celii
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Publication number: 20100176427Abstract: A method of manufacturing a semiconductor device. The method comprises fabricating a ferroelectric capacitor. The capacitor's fabrication includes forming conductive and ferroelectric material layers on a semiconductor substrate, forming a hardmask layer on the conductive and ferroelectric material layers, forming an organic bottom antireflective coating layer on the hardmask layer, and, patterning the organic bottom antireflective coating layer. Seasoning in a hardmask etching chamber is substantially unaffected by the patterning.Type: ApplicationFiled: January 13, 2009Publication date: July 15, 2010Applicant: Texas Instruments IncorporatedInventor: Francis Gabriel Celii
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Patent number: 7723199Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.Type: GrantFiled: January 31, 2007Date of Patent: May 25, 2010Assignee: Texas Instruments IncorporatedInventors: Yaw S. Obeng, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Sanjeev Aggarwal, Francis Gabriel Celii, Lindsey H. Hall, Robert Kraft, Theodore S. Moise
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Publication number: 20090194801Abstract: A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.Type: ApplicationFiled: February 4, 2008Publication date: August 6, 2009Applicant: Texas Instruments Inc.Inventors: Francis Gabriel Celii, Robert Kraft, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Theodore S. Moise
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Publication number: 20080081380Abstract: A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.Type: ApplicationFiled: February 15, 2007Publication date: April 3, 2008Inventors: Francis Gabriel Celii, Kezhakkedath R. Udayakumar, Gregory B. Shinn, Theodore S. Moise, Scott R. Summerfelt
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Publication number: 20070298521Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.Type: ApplicationFiled: January 31, 2007Publication date: December 27, 2007Applicant: Texas Instruments IncorporatedInventors: Yaw S. Obeng, Kezhakkedath R. Udayakumar, Scott Robert Summerfelt, Sanjeev Aggarwal, Francis Gabriel Celii, Lindsey H. Hall, Robert Kraft, Theodore S. Moise
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Patent number: 6841396Abstract: A ferroelectric memory device comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereof for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and reference voltage on the second bit line.Type: GrantFiled: May 19, 2003Date of Patent: January 11, 2005Assignee: Texas Instruments IncorporatedInventors: Francis Gabriel Celii, K. R. Udayakumar, Scott R. Summerfelt, Theodore S. Moise
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Publication number: 20040235259Abstract: A ferroelectric memory device is disclosed and comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.Type: ApplicationFiled: May 19, 2003Publication date: November 25, 2004Inventors: Francis Gabriel Celii, K. R. Udayakumar, Scott R. Summerfelt, Theodore S. Moise
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Publication number: 20040072442Abstract: One aspect of the invention relates to a method of manufacturing FeRAM, and in particular, plasma etching a bottom electrode layer in a ferroelectric capacitor stack. According to the method, plasma etching is carried out at a relatively low bias in an atmosphere that includes a halogen compound and an oxygen source containing carbon, such as carbon monoxide or carbon dioxide. The invention prevents shorting along the sidewalls of the capacitor stack, which can otherwise be caused by re-deposition of material released from the bottom electrode layer. The gas composition and temperature are such that chemical reaction substantially contributes to the etch rate as compared to purely physical etching. In one embodiment, the capacitor stack is etched with a hard mask that include TiAlN and the atmosphere is oxidizing to an extent that increases the selectivity between the hard mask and the bottom electrode layer.Type: ApplicationFiled: October 15, 2002Publication date: April 15, 2004Inventors: Francis Gabriel Celii, Mahesh Thakre, Scott R. Summerfelt