Abstract: A synchronous dynamic random access memory (SDRAM) is disclosed that includes an operational mode in which the functionality of the SDRAM can be tested under burn-in conditions. The SDRAM can be placed in a burn-in monitor mode in which burn-in information is provided at data outputs, in lieu of memory cell information. The burn-in monitor mode helps to ensure that the SDRAM functions are properly exercised during burn-in. The preferred embodiment includes a data buffer coupled to a data bus and a mode register. The mode register stores burn-in mode data. In a standard mode of operation, the data buffer couples the data bus to data outputs (D0-Dz). In a burn-in monitor mode of operation, the data buffer couples the burn-in mode data to the data outputs (D0-Dz).

Abstract: Programmable time delay apparatus includes a plurality of similar components (10) which determine the total time delay of the apparatus. These components have gate units (31.sub.0 -31.sub.n, 32.sub.0 -32.sub.n, 33.sub.0 -33.sub.n, 34.sub.0 -34.sub.n) coupled thereto which, in response to a control signal (b.sub.0 -b.sub.n) applied to each component, either electrically couples the component to the apparatus or electrically removes of the component from the apparatus. In a first embodiment, the control signals (b.sub.0 -b.sub.n) place time delay components (10) in a series configuration, the total time delay being the sum of the time delays of each series-coupled component (10). In the second and third embodiment, the resistors (47.sub.0 -47.sub.n) and the capacitors (53.sub.0 -53.sub.n), respectively, are coupled in a capacitance charging circuit (47.sub.0 -47.sub.n, 43; 52, 53.sub.0 -53.sub.n), the coupled elements controlling the charging rate and, consequently, the time delay of the apparatus.

Abstract: Programmable time delay apparatus includes a plurality of similar components (10) which determine the total time delay of the apparatus. These components have gate units (31.sub.0 -31.sub.n,32.sub.0 -=.sub.n, 33.sub.0 -33.sub.n, 34.sub.0 -34.sub.n) coupled thereto which, in response to a control signal (b.sub.0 -b.sub.n) applied to each component, either electrically couples the component to the apparatus or electrically removes of the component from the apparatus. In a fist embodiment, the control signals (b.sub.0 -b.sub.n) place time delay components (10) in a series configuration, the total time delay being the sum of the time delays of each series-coupled component (10). In the second and third embodiment, the resistors (47.sub.0 -47.sub.n) and the capacitors (53.sub.0 -53.sub.n), respectively, are coupled in a capacitance charging circuit (47.sub.0 -47.sub.n, 43; 52, 53.sub.0 -53.sub.n), the coupled elements controlling the charging rate and, consequently, the time delay of the apparatus.

Abstract: A circuit for selecting a block spare in a semiconductor device is designed with a programmable circuit (14), storing an internal address and producing an address match signal AM and a block select signal BS in response to first (A) and second (B) address signals and the internal address. A global spare circuit (28) produces a global spare select signal (GSS), in response to the address match signal. A block spare circuit (34) produces a block spare select signal (BSS), in response to the global spare select signal and the block select signal.

Abstract: A circuit for selecting a block spare in a semiconductor device is designed with a programmable circuit (14), storing an internal address and producing an address match signal AM and a block select signal BS in response to first (A) and second (B) address signals and the internal address. A global spare circuit (28) produces a global spare select signal (GSS), in response to the address match signal. A block spare circuit (34) produces a block spare select signal (BSS), in response to the global spare select signal and the block select signal.

Abstract: A device tester provides signals to a device under test. A parallel compare circuit then receives all the outputs of the device and compares each of the outputs with one another simultaneously. Next the parallel compare circuit will produce an output pattern which is compared to the expected test pattern stored in the tester. If the output pattern from the parallel compare circuit is the same as the expected test pattern the device will be considered a properly working device; conversely, if the patterns do not match the device will be considered an improperly working device.