Abstract: A multiplier of order p and of depth n+1 is formed by a root R constituted by a carry-save adder and by a multiplier body CO(p,n) of order p and of depth n formed by a five-input connector operator C(n,q) of rank q, the connector operator C(n,1) of rank 1 is connected to the root R, the connector operator C(n,q) of rank q comprising first and second carry-save adders (1, 2) connected in cascade. The multiplier body CO(p,n) further includes a tree A(p-1,n-2) of order p-1 and of depth n-2 formed by an arrangement of carry-save adders and connected to the first carry-save adder (1), and a multiplier body CO(p,n-1 ) of order p and of lesser depth n-1 formed analogously to the multiplier body CO(p,n) of greater depth n by recurrence, the multiplier body CO(p,n-1) of lesser depth being connected to the connector operator C(n,q). The multiplier is applicable to performing calculations and to implementing digital filters.

Abstract: A method and circuit for processing digital signals representative of vectors that permits processing between pairs of vectors of sets of vectors for ensuring the meeting in space and time of these vectors. This meeting is effected using parallel processing in a two-dimensional network of cells for processing the component assigned to a dimension of the network, and sequentially by partitioning the sets into sub-sets subjected to processing during a microcycle, during which a sub-set is stored. A sub-set is stored during a macrocycle for the next processing and so on. Vectors can consist of tuples of a data base.

Abstract: The invention relates to encoding a digital signal to determine the scalar product of two vectors. For two vectors of the same dimension p, one having dedicated components {ak} and the other having variable components {xk}, the scalar product value ##EQU1## is reduced to partial sums fi of binary variables xki, which binary variables take one of the values of the fixed components ak depending on the values of the xki having m possible values. Dedicated logic encoding makes it possible to take the variables xki and generate a plurality of bit level elementary partial sums fij for each bit of rank j in fi, having 2.sup.m possible values, by varying the binary values akj of the bits of rank j. A two-dimensional interconnection matrix causes each rank j bit akj to correspond to a single value of the elementary partial sums fij, and together these bits define the corresponding partial sum fi. The invention is applicable to circuits for image processing or for data compression by the discrete cosine transform.

Abstract: For processing data signals representative of pixels, each of the pictures s scanned, column per column in successive horizontal bands each having a height equal to an entire fraction of the height of the picture, whereby a representation of the picture as pixels distributed in rows and columns is obtained, each band having a common predetermined number of rows. The picture is fractionated into mutually adjacent blocks of pixels each having M pixels in each of N mutually adjacent columns, M and N being predetermined integers and M being a simple multiple of the number of pixels in one column of a band and N being a whole fraction of the number of colums per image.

Abstract: For filtering a bi-dimensional image signal in the form of data representing pixels obtained by column per column scanning of bands each having a height equal to a fraction of the height of the image, the transform of each pixel is computed in turn. For that, a convolution product using MxN coefficients is carried out on the pixels of a zone of an image, each column of each M pixels. The image is fractionated into mutually adjacent blocks each representing N columns of M pixels and the transforms of all pixels of a same block are simultaneously computed in MxN cycles by: parallel computation, during a same cycle, of all partial convolution products of only one of the filtering coefficients and of those pixels which provide a partial product which intervenes in the computation of the transforms of all pixels of the block, within a "window" of the picture which contains the block. The cycle is repeated for each coefficient in turn. All partial products obtained during the successive cycles are summed.

Abstract: A recursive type adder for calculating the sum of two operands. It is used to calculate the sum of two binary data numbers using adders in the form of integrated circuits, particularly for information processing systems wherein the adders constitute one of the fundamental operations of data processing. The invention is classified in the category of parallel-parallel type adders.

Abstract: A circuit which performs a linear transformation on a digital signal. A linear transformation is defined by a graph whose nodes represent operations of addition or subtraction and the branches operations of multiplication by a determined coefficient. According to the invention, the circuit comprises a multiplier for each branch, this multiplier being wired according to the value of the determined coefficient of said branch, and an adder for each node, each adder being wired according to the nature of the operation, addition or subtraction, associated with said node.

Abstract: Binary adder having a fixed operand and a parallel-serial binary multiplier incorporating such an adder. The multiplier comprises a dedicated adder, whose elements (transistors, logic gates, etc.) are wired to incorporate the value of the fixed operand B. The non-fixed operand D is applied in serial form to the control input of a multiplexer. The multiplier also comprises an accumulator-shift register for storing a partial result A of the multiplication. As a function of the state of the multiplexer, the register receives A or A+B.