Abstract: A bale accumulator for grouping bales for group baling includes a platform, a depositor mounted adjacent to the platform for sequentially depositing bale sets onto the platform, each bale set when deposited onto the platform comprises a pair of bales positioned upright and side-by-side in a packing orientation so that their corresponding long sides are axially juxtaposed, and a packer apparatus mounted adjacent to the platform for packing one bale set at a time from the platform into a group baler trailing the platform each time a bale set is deposited onto the platform from the depositor without changing the packing orientation of the bales of each bale set.

Abstract: A bale accumulator for grouping bales for group baling includes a platform, a depositor mounted adjacent to the platform for sequentially depositing bale sets onto the platform, each bale set when deposited onto the platform comprises a pair of bales positioned upright and side-by-side in a packing orientation so that their corresponding long sides are axially juxtaposed, and a packer apparatus mounted adjacent to the platform for packing one bale set at a time from the platform into a group baler trailing the platform each time a bale set is deposited onto the platform from the depositor without changing the packing orientation of the bales of each bale set.

Abstract: A bale accumulator for grouping bales for group baling includes a platform, a depositor mounted adjacent to the platform for sequentially depositing bale sets onto the platform, each bale set when deposited onto the platform comprises a pair of bales positioned upright and side-by-side in a packing orientation so that their corresponding long sides are axially juxtaposed, and a packer apparatus mounted adjacent to the platform for packing one bale set at a time from the platform into a group baler trailing the platform each time a bale set is deposited onto the platform from the depositor without changing the packing orientation of the bales of each bale set.

Abstract: A bale accumulator for grouping bales for group baling includes a platform, a depositor mounted adjacent to the platform for sequentially depositing bale sets onto the platform, each bale set when deposited onto the platform comprises a pair of bales positioned upright and side-by-side in a packing orientation so that their corresponding long sides are axially juxtaposed, and a packer apparatus mounted adjacent to the platform for packing one bale set at a time from the platform into a group baler trailing the platform each time a bale set is deposited onto the platform from the depositor without changing the packing orientation of the bales of each bale set.

Abstract: A bale accumulator for grouping bales for group baling includes a platform, a depositor mounted adjacent to the platform for sequentially depositing bale sets onto the platform, each bale set when deposited onto the platform comprises a pair of bales positioned upright and side-by-side in a packing orientation so that their corresponding long sides are axially juxtaposed, and a packer apparatus mounted adjacent to the platform for packing one bale set at a time from the platform into a group baler trailing the platform each time a bale set is deposited onto the platform from the depositor without changing the packing orientation of the bales of each bale set.

Abstract: A programmable equalizer and related method are provided. The equalizer includes a pair of current-setting field effect transistors (FETs) coupled in series with a pair of input FETs and a pair of load resistors, respectively, between a first voltage rail (Vdd) and a second voltage rail (ground). A programmable equalization circuit is coupled between the sources of the input FETs, comprising a plurality of selectable resistive paths and a variable capacitor, which could also be configured as a plurality of selectable capacitive paths. Each of the selectable resistive paths (as well as each of the selectable capacitive paths) include a selection FET for selectively coupling the corresponding resistive (or capacitive) path between the sources of the input FETs. In the case where one of the input FETs is biased with a reference gate voltage, the source of each selection FET is coupled to the source of such input FET.

Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

Abstract: A programmable equalizer and related method are provided. The equalizer includes a pair of current-setting field effect transistors (FETs) coupled in series with a pair of input FETs and a pair of load resistors, respectively, between a first voltage rail (Vdd) and a second voltage rail (ground). A programmable equalization circuit is coupled between the sources of the input FETs, comprising a plurality of selectable resistive paths and a variable capacitor, which could also be configured as a plurality of selectable capacitive paths. Each of the selectable resistive paths (as well as each of the selectable capacitive paths) include a selection FET for selectively coupling the corresponding resistive (or capacitive) path between the sources of the input FETs. In the case where one of the input FETs is biased with a reference gate voltage, the source of each selection FET is coupled to the source of such input FET.

Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

Abstract: A circuit includes a first die having a first array of exposed data nodes, and a second die having a second array of exposed data nodes, wherein a given data node of the first array corresponds to a respective data node on the second array, further wherein the first array and the second array share a spatial arrangement of the data nodes, wherein the first die has data inputs and sequential logic circuits for each of the data nodes of the first array on a first side of the first array, and wherein the second die has data outputs and sequential logic circuits for each of the data nodes of the second array on a second side of the second array, the first and second sides being different.

Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

Abstract: A device for acoustic or electronic drum sets is described comprising at least a first throne section and two extending portions for accommodating drum sets or components thereof placed thereon. A particular embodiment comprises a throne section that defines a built in drum key pocket; two extensions rotatably and extendibly coupled to the throne section that can expand and collapse at least partially to accommodate drum sets or components thereof placed thereon and to facilitate transportation, at least one of the two extensions defining a handle for carrying the device; first and second arm extensions rotatably coupled to each of the two extensions; and plural levelers for leveling the device. The drum device can be configured to receive a single bass drum and single bass drum pedal; configured for use with a single bass drum and double bass drum pedal; or configured for use with a double bass drum and bass drum pedals.