Patents by Inventor Francis Masiglat de Vera

Francis Masiglat de Vera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230386979
    Abstract: In a described example, an apparatus includes: a semiconductor die having a device side surface and an opposing backside surface, the backside surface mounted to a die pad of a lead frame using a die attach film; bond pads overlying the device side surface of the semiconductor die; bond wires electrically coupling the bond pads to leads of the lead frame spaced from the die pad; and mold compound covering the semiconductor die, the bond wires, and portions of the lead frame, where portions of the leads are exposed from the mold compound to form terminals of the packaged semiconductor device. The die attach film has a partially cut die attach film layer with a cut side edge normal to the backside surface, and the die attach film has an uncut die attach film layer with a torn side edge normal to the backside surface.
    Type: Application
    Filed: May 31, 2022
    Publication date: November 30, 2023
    Inventors: Jesus Bajo Bautista, Jeniffer Otero Aspuria, Jezreel Duane Caluza Aquino, Francis Masiglat de Vera
  • Publication number: 20230207390
    Abstract: A method includes applying laser pulses along a direction to a side of a wafer to create first and second stealth damage regions at respective first and second depths in the wafer and to create cracks that extend in the wafer from the respective stealth damage regions and that are spaced apart from one another along the direction, applying a compressive and retractive cyclical force to the wafer along the third direction to propagate and join the cracks from the respective stealth damage regions together, and expanding the wafer to separate individual dies from the wafer.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Jesus Bajo Bautista, JR., Jeniffer Otero Aspuria, Francis Masiglat de Vera
  • Publication number: 20220157678
    Abstract: Integrated circuit packaging with cavities and methods of manufacturing the same are disclosed. An example apparatus includes a semiconductor die and a housing enclosing portions of the semiconductor die. The housing defines an opening that extends from a surface of the semiconductor die to an external environment, the housing formed of a first material. The example apparatus includes a second material disposed within the opening to block exposure of the semiconductor die to the external environment.
    Type: Application
    Filed: January 27, 2022
    Publication date: May 19, 2022
    Inventors: Jesus Bajo Bautista, Jr., Jeffrey Dorado Emperador, Francis Masiglat de Vera
  • Publication number: 20190206752
    Abstract: Integrated circuit packaging with cavities and methods of manufacturing the same are disclosed. An example apparatus includes a semiconductor die and a housing enclosing portions of the semiconductor die. The housing defines an opening that extends from a surface of the semiconductor die to an external environment, the housing formed of a first material. The example apparatus includes a second material disposed within the opening to block exposure of the semiconductor die to the external environment.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Jesus Bajo Bautista, JR., Jeffrey Dorado Emperador, Francis Masiglat de Vera