Abstract: A novel and useful variable delay digitally controlled crystal oscillator (DCXO) buffer (i.e. slicer). A conventional slicer following the DCXO is modified to introduce a controlled random variable delay into the buffered DCXO clock. The resultant output clock signal is then used as input to the TDC of an ADPLL circuit to alleviate the subharmonic mixing based deterioration caused by LO/TX coupling through the crystal pins, and to alleviate the dead-beat effects caused by the finite resolution of the TDC. Two mechanisms for introducing variable delay into the buffered DCXO output clock signal are presented: a first mechanism that creates variable delay in fine steps and a second mechanism that creates variable delay in coarse steps. In both mechanisms, switches are incorporated into the slicer circuitry and controlled using digital bit sequences which may comprise dithering signals.

Abstract: A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high.

Abstract: A novel apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art analog quadrature modulator structures and those based on a digital polar architecture (r, ?). The modulator effectively operates as a complex digital-to-analog converter where the digital inputs are given in Cartesian form, namely I and Q representing the complex number I+jQ, while the output is a modulated RF signal having a corresponding amplitude and phase shift. The phase shift being with respect to a reference phase dictated by the local oscillator, which is also input to the converter/modulator. Several embodiments are provided including modulators incorporating dual I and Q transistor arrays, a single shared I/Q transistor array, modulators with single ended and differential outputs and modulators with single and dual polarity clock and I/Q data signals.

Abstract: A novel and useful variable delay digitally controlled crystal oscillator (DCXO) buffer (i.e. slicer). A conventional slicer following the DCXO is modified to introduce a controlled random variable delay into the buffered DCXO clock. The resultant output clock signal is then used as input to the TDC of an ADPLL circuit to alleviate the subharmonic mixing based deterioration caused by LO/TX coupling through the crystal pins, and to alleviate the dead-beat effects caused by the finite resolution of the TDC. Two mechanisms for introducing variable delay into the buffered DCXO output clock signal are presented: a first mechanism that creates variable delay in fine steps and a second mechanism that creates variable delay in coarse steps. In both mechanisms, switches are incorporated into the slicer circuitry and controlled using digital bit sequences which may comprise dithering signals.