Abstract: Phase slippage of a test clock signal and the direction of such slippage are digitally detected, accumulated, and displayed and/or recorded. A test clock signal is recovered from one digital carrier signal. A reference clock signal is recovered from another digital carrier signal. From the test clock signal, first and second binary signals are generated at a frequency phase synchronized to the test clock signal. The second signal is shifted in phase from the first signal. Responsive to the reference clock signal, the states of the first and second signals are repeatedly sampled such that the sampled states are representative of the phase relationship between the test clock signal and the reference clock signal. Successive samples of the states of the first and second signals are compared to detect unit interval phase shifts between the test clock signal and the reference clock signal. The phase shifts detected by the comparison are accumulated at successive samples are compared to represent phase slippage.

Abstract: Phase slippage of a test clock signal and the direction of such slippage are digitally detected, accumulated, and displayed and/or recorded. A test clock signal is recovered from one digital carrier signal. A reference clock signal is recovered from another digital carrier signal. From the test clock signal, first and second binary signals are generated at a frequency phase synchronized to the test clock signal. The second signal is shifted in phase from the first signal. Responsive to the reference clock signal, the states of the first and second signals are repeatedly sampled such that the sampled states are representative of the phase relationship between the test clock signal and the reference clock signal. Successive samples of the states of the first and second signals are compared to detect unit interval phase shifts between the test clock signal and the reference clock signal. The phase shifts detected by the comparison are accumulated at successive samples are compared to represent phase slippage.

Abstract: A source of a duobinary data signal is connected to a remote point by a coupling network having a high pass characteristic and transmission line. The data signal received at the remote point is subtracted from a delayed version thereof to derive the change representative signal, which is utilized at the remote point to regenerate and/or detect code violations of the data signal. Preferably, the received data signal is subtracted from a version thereof delayed by one bit time period. Circuitry generates an indication of a violation when, after assuming one extreme level in a given bit time period, the change representative signal again assumes the same level before assuming the other extreme level during a bit time period separated by an odd number of bit time periods from the given bit time period. Circuitry may also convert the change representative signal back to the duobinary data signal.

Abstract: A telephone line holding circuit is disclosed which is adapted for temporary connection across a telephone line to maintain that line in a hold condition while line measurements and tests are being performed. The holding circuit is designed to be used over a wide range of line supply voltages and line resistances without introducing line measurement errors. The holding circuit includes a current regulator which maintains the line current at a predetermined level as long as the voltage appearing across the line remains above a predetermined voltage level. The holding circuit also includes a voltage regulator which reduces the predetermined current level to a value which prevents the average line voltage from being reduced below the predetermined voltage level. The holding circuit further includes circuit elements for protecting the circuit elements from damage caused by the application of excessive voltage on the line.