Patents by Inventor Francis W. Wiedman, III

Francis W. Wiedman, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4380057
    Abstract: An electrically alterable double dense memory is provided which includes a field effect transistor having first and second spaced apart diffusion regions of a first conductivity defining a channel region at the surface of a semiconductor substrate having a second conductivity. First and second floating gates are disposed over the first and second diffusion regions, respectively, and each extends over an end of the channel region. First and second dual charge injector structures or enhanced conduction insulators are disposed between the first and second floating gates and a common control gate of the transistor. A word line is connected to the control gate and first and second bit lines are connected to the first and second diffusion regions. By applying appropriate pulses to the word and bit lines, a selected floating gate can be charged to alter the conductivity of the end of the channel region associated with the selected floating gate and then discharged at will.
    Type: Grant
    Filed: October 27, 1980
    Date of Patent: April 12, 1983
    Assignee: International Business Machines Corporation
    Inventors: Harish N. Kotecha, Wendell P. Noble, Jr., Francis W. Wiedman, III
  • Patent number: 4336603
    Abstract: A memory system is provided for charging and discharging small cells each of which has only three terminals with a charge injector controlled by a low single polarity voltage. Each of the cells includes a transistor having a current carrying electrode and a floating gate, with a control gate arranged so that a first capacitor is serially connected with a second capacitor between the current carrying electrode and the control gate, with one of the capacitors having a substantially larger capacitance than that of the other capacitor and with the other capacitor including a charge injector. The common point between the first and second capacitors is connected to the floating gate. The charge injector may include a single graded or stepped composition region or two such regions disposed near opposite faces or plates of the other capacitor, or more particularly the injector may include silicon rich regions near one or both faces of a layer of silicon dioxide.
    Type: Grant
    Filed: June 18, 1980
    Date of Patent: June 22, 1982
    Assignee: International Business Machines Corp.
    Inventors: Harish N. Kotecha, Francis W. Wiedman, III
  • Patent number: 4190466
    Abstract: A semiconductor structure, formed within a recessed oxide isolation region, includes a semiconductor substrate of a first conductivity type within which a collector of opposite conductivity type is formed below the surface of the substrate and extending in part to the surface of the substrate for ease of contact. A first layer of doped polycrystalline silicon or polysilicon is formed on a first portion of the surface of the substrate and in electrical contact with the substrate which acts as the base of a transistor. The first polysilicon layer is oxidized to form an outer insulating layer thereover. A second doped polysilicon layer is disposed over the outer insulating layer onto a second portion of the surface of the substrate so as to be spaced from the first portion by only the thickness of the outer insulating layer on the first polysilicon layer. The dopant in the second polysilicon layer is driven into the surface of the semiconductor substrate to form an emitter therein.
    Type: Grant
    Filed: December 22, 1977
    Date of Patent: February 26, 1980
    Assignee: International Business Machines Corporation
    Inventors: Arup Bhattacharyya, Francis W. Wiedman, III