Abstract: A window comparator is disclosed having a 1st and a 2nd voltage input wherein the window comparator is fully differential with respect to the 1st and 2nd voltage inputs. Two differential pairs control the state of a zero-crossing comparator in response to the difference between the 1st and 2nd voltage inputs.

Abstract: A voltage-controlled oscillator auto-calibrating system is disclosed that performs center-frequency calibration of a VCO. A frequency range detector monitors the VCO frequency and provides coarse adjustments so that the target frequency is within the capture range of the VCO's fine-tuning voltage. A lock detector monitors the phase-locked loop circuit and triggers an adjustment after the phase-locked loop circuit achieves lock. A monotonicity check circuit provides VCO frequency adjustments so that the VCO's fine-tuning frequency range is centered approximately around the target frequency.

Abstract: A voltage-controlled oscillator frequency range detector is disclosed that detects when the voltage-controlled oscillator frequency within a phase-locked loop is out of range and indicates the required direction of the frequency adjustment. The voltage-controlled oscillator frequency range detector includes a comparator circuit, which receives a voltage-controlled oscillator control voltage signal, and a frequency detector circuit, which receives a reference clock signal and a voltage-controlled oscillator clock signal. Decision logic circuitry, coupled to the comparator circuit and to the frequency detector circuit, receives at least one output from the comparator circuit and an output from the frequency detector circuit and indicates whether an adjustment to a voltage-controlled oscillator frequency is required and its direction.

Abstract: A leakage current compensation system and method is disclosed that reduces frequency spurs and phase offset in a frequency synthesizer. The leakage current is determined based on the phase offset of the frequency synthesizer relative to a reference clock. A leakage current compensation circuit provides a leakage current compensation signal to the frequency synthesizer at the loop filter terminals to minimize the phase offset.

Abstract: A dual phase locked loop (PLL) lock detector is disclosed using a single lock detector to determine whether a dual PLL system is in a lock condition. In one embodiment, a VCO clock output from a master PLL is frequency divided to form a reference clock for a slave PLL. The lock detector monitors the slave PLL only when it determines that the master PLL is locked.