Abstract: A wireless transmitter processing chain includes digital radio frequency mixing circuitry to generate, in digital form, a representation of a transmit signal including multiple communication channels. From the digital representation, a wideband digital to analog converter creates the analog transmit signal that includes the communication channels. Individual mixers and filters follow, with mixing frequencies tuned to place the communication channels at the desired frequency centers.

Abstract: A wireless transmitter processing chain includes digital radio frequency mixing circuitry to generate, in digital form, a representation of a transmit signal including multiple communication channels. From the digital representation, a wideband digital to analog converter creates the analog transmit signal that includes the communication channels. Individual mixers and filters follow, with mixing frequencies tuned to place the communication channels at the desired frequency centers.

Abstract: A wireless transmitter processing chain includes digital radio frequency mixing circuitry to generate, in digital form, a representation of a transmit signal including multiple communication channels. From the digital representation, a wideband digital to analog converter creates the analog transmit signal that includes the communication channels. Individual mixers and filters follow, with mixing frequencies tuned to place the communication channels at the desired frequency centers.

Abstract: A wireless transmitter processing chain includes digital radio frequency mixing circuitry to generate, in digital form, a representation of a transmit signal including multiple communication channels. From the digital representation, a wideband digital to analog converter creates the analog transmit signal that includes the communication channels. Individual mixers and filters follow, with mixing frequencies tuned to place the communication channels at the desired frequency centers.

Abstract: A transmitter's operation is characterized using components having relatively low cost and low complexity. A device includes comparator(s) that compare a transmitter's analog output to predetermined level(s) to generate count(s) associated with analog output range bin(s). Each of the predetermined levels is associated with a corresponding one of the analog output range bins. A transfer function of the transmitter is generated using the comparison count values associated with the analog output range bin(s). A histogram may be generated from the comparison count values associated with the various analog output range bins. An equalizer is implemented to process data that will be transmitted by the transmitter. The equalizer uses equalizer parameter(s) that are selected based on the characterization of the transmitter (e.g., its transfer function, its histogram, etc.). The equalizer may use default or start up parameters until the transmitter's operation is characterized.

Abstract: A system may include a first stage comprising first signaling components for a first protocol, and a second stage comprising second signaling components for the first protocol and a second protocol. The system may further include logic configured to receive an incoming data stream, and determine a stream protocol for the data stream. The logic may be further configured to, responsive to the determination, activate the at least a portion of the first stage when the stream protocol is compliant with the first protocol, and when the stream protocol is compliant with the second protocol, deactivate the first stage.

Abstract: A transmitter's operation is characterized using components having relatively low cost and low complexity. A device includes comparator(s) that compare a transmitter's analog output to predetermined level(s) to generate count(s) associated with analog output range bin(s). Each of the predetermined levels is associated with a corresponding one of the analog output range bins. A transfer function of the transmitter is generated using the comparison count values associated with the analog output range bin(s). A histogram may be generated from the comparison count values associated with the various analog output range bins. An equalizer is implemented to process data that will be transmitted by the transmitter. The equalizer uses equalizer parameter(s) that are selected based on the characterization of the transmitter (e.g., its transfer function, its histogram, etc.). The equalizer may use default or start up parameters until the transmitter's operation is characterized.

Abstract: The invention refers to signal processing circuits, more particularly, to switch capacitor circuits, and methods for reducing inter-symbol-interference. A switch capacitor circuit with reduced Inter-Symbol-Interference effect is provided, comprising: a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect.

Abstract: A programmable gain attenuator (PGA) in particular to be used in a track-and-hold circuit is disclosed. The PGA is located in the feedback path around an operational amplifier. One tap switch is used to connect one PGA section to the output of the operational amplifier. The PGA section is capable of producing a multiplicity of different gain settings by using a multiplicity of secondary resistive devices in a voltage divider, wherein the resistive devices each can be independently coupled to a reference voltage.

Abstract: A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.

Abstract: A voltage domain crossing circuit and method are disclosed. In one embodiment, the voltage domain crossing circuit comprises an AC coupling component, a DC biasing component and a high voltage output amplifier. The AC coupling component receives an input low voltage signal and AC couples and splits the signal into two voltages. The two voltages are then DC biased to a predetermined bias voltage using the DC biasing component. The high voltage output amplifier then amplifies the biased voltages in the high voltage domain yielding a signal in the high voltage domain. Other embodiments of the voltage domain crossing circuit and method are also disclosed.

Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on.

Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.

Abstract: A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.

Abstract: A differential comparator with improved bit-error rate performance operating with a low supply voltage. The differential comparator includes a first pair of transistors receiving a differential input. A second pair of transistors is coupled to the first pair of transistors. A pair of resistive elements is connected between the first pair and second pair of transistors so as to increase bias currents shared by the first and second pairs of transistors. The increased bias currents reduce a time required by the differential comparator to transition from a meta-stable state to a stable state, thereby improving a bit-error rate of the differential comparator. The resistive elements can use linear resistors or transmission gates. Gates of either the first or second pair of transistors can provide an output.

Abstract: The invention refers to signal processing circuits, more particularly, to switch capacitor circuits, and methods for reducing inter-symbol-interference. A switch capacitor circuit with reduced Inter-Symbol-Interference effect is provided, comprising: a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way that the first capacitor is charged to a first voltage by means of the voltage source, and then discharged by means of the second capacitor, thereby reducing the Inter-Symbol-Interference effect.

Abstract: A voltage domain crossing circuit and method are disclosed. In one embodiment, the voltage domain crossing circuit comprises an AC coupling component, a DC biasing component and a high voltage output amplifier. The AC coupling component receives an input low voltage signal and AC couples and splits the signal into two voltages. The two voltages are then DC biased to a predetermined bias voltage using the DC biasing component. The high voltage output amplifier then amplifies the biased voltages in the high voltage domain yielding a signal in the high voltage domain. Other embodiments of the voltage domain crossing circuit and method are also disclosed.

Abstract: A programmable gain attenuator includes a termination resistor. A first termination switch connects one side of the termination resistor to a first output. A second termination switch connects another side of the termination resistor to a second output. A first resistor ladder is arranged between a first input and the first side of the termination resistor. A first plurality of switches connect a corresponding tap from the first resistor ladder to the first output. A second resistor ladder is arranged between a second input and the second side of the termination resistor. A second plurality of switches connect a corresponding tap from the second resistor ladder to the second output. A first switch of the first plurality of switches is turned on, followed by a second switch of first plurality of switches turned off, followed by a third switch of first plurality of switches turned on.

Abstract: A differential multiplexer includes a plurality of multiplexing circuits. Each multiplexing circuit inputs a corresponding differential input signal including a positive input signal and a negative input signal, and outputs positive and negative output signals. Each multiplexing circuit includes first, second, third and fourth transistors. The first and second transistors input the positive input signal. The third and fourth transistors input the negative input signal. Outputs of the first and third transistors are connected to the positive output signal. Outputs of the second and fourth transistors are connected to the negative output signal. The positive and negative output signals are controlled using gate voltages on the first and fourth transistors. The second and third transistors are turned off when the differential multiplexer is in use. The transistors are cross-coupled to make leakage between the positive and negative input signals common mode in the positive and negative output signals.

Abstract: A differential multiplexer includes a plurality of multiplexing circuits. Each multiplexing circuit inputs a corresponding differential input signal including a positive input signal and a negative input signal, and outputs positive and negative output signals. Each multiplexing circuit includes first, second, third and fourth transistors. The first and second transistors input the positive input signal. The third and fourth transistors input the negative input signal. Outputs of the first and third transistors are connected to the positive output signal. Outputs of the second and fourth transistors are connected to the negative output signal. The positive and negative output signals are controlled using gate voltages on the first and fourth transistors. The second and third transistors are turned off when the differential multiplexer is in use. The transistors are cross-coupled to make leakage between the positive and negative input signals common mode in the positive and negative output signals.