Abstract: A semiconductor device includes a semiconductor body (1) which is provided at a surface (2) with a non-volatile memory cell comprising a source (3) and a drain (4), and an access gate (14) which is electrically insulated from a gate structure (8) comprising a control gate (9), the gate structure (8) being electrically insulated from the semiconductor body (1) by a gate dielectric (11,25). The gate dielectric (11,25) is provided with a charge-storage region wherein data in the form of electric charge can be stored. The access gate (14) has a substantially flat surface portion (17) extending substantially parallel to the surface (2) of the semiconductor body (1) and has the shape of a block which is disposed against the gate structure (8) without overlapping the gate structure (8).

Abstract: Two substantially identical currents (I1,a, I1,b) are subtracted from each other, while being generated by elements (10, 11) in such a way that noise in the current value of said two currents (I1,a, I1,b) is determined by shot noise. The differential current, determined only by shot noise, is supplied to a capacitor (13). A second current (I2) is used to charge a second capacitor (22, 29). It is periodically determined whether the value of a voltage across the first capacitor (13) is within or outside a range bounded by the (negative and positive values of the) voltage of the second capacitor (22, 29) which has been charged over the same period of time. The currents (I1,b, Ib) are set in dependence on the result of the comparison. The signal to set the currents (I1,b, Ib) also serves as control signal for an element (43) connected as a constant current source.

Abstract: A semiconductor device comprising a non-volatile memory cell, for storing at least one bit, in a semiconductor substrate (1) having, in the substrate, a source region (6), a drain region (7) and a channel region (10) between the source (6) and drain (7) regions, and having, on top of the substrate, a floating gate (9) separated from the channel region (10) by a floating gate insulating layer, a select gate (11) adjacent to the floating gate and separated from the channel region by a select gate insulating layer (8), and a control gate (5) separated from the floating gate (9) by a control gate insulating layer, the floating gate being a non-conducting charge trapping dielectric layer (9).

Abstract: A data processing device has a memory with writeable and erasable locations, such as a flash memory. The memory locations are store WOM codewords (Write Once Memory codewords in which successive generations of data can be encoded by setting bits from zero to one only). A data encoder encodes a received data value in a new codeword from the WOM code, as a function of the received data value and a previous codeword stored in the currently selected location. When the WOM codeword is exhausted the data encoder selects a new currently selected location from a logical series of locations and stores the new codeword in the new currently selected location. When all locations are exhausted a reset circuit resets a content of the locations in the logical series. On reading the currently selected location is read and decoded.

Abstract: A semiconductor device comprises a semiconductor body (1) which is provided at a surface (2) with a non-volatile memory cell comprising a source (3) and a drain (4), and an access gate (14) which is electrically insulated from a gate structure (8) comprising a control gate (9), the gate structure (8) being electrically insulated from the semiconductor body (1) by a gate dielectric (11, 25). The gate dielectric (11, 25) is provided with a charge-storage region wherein data in the form of electric charge can be stored. The access gate (14) has a substantially flat surface portion (17) extending substantially parallel to the surface (2) of the semiconductor body (1) and has the shape of a block which is disposed against the gate structure (8) without overlapping the gate structure (8).

Abstract: One-time UV-programmable read-only memory (1) comprising a number of memory cells in the form of MOS transistors (T) which are arranged in a matrix of rows and columns, each transistor comprising a source and a drain zone (12) and a channel zone (13) formed in a surface zone (11) of a semiconductor substrate (10). Said semiconductor zones adjoin a surface (14) of the semiconductor substrate on which surface a layer structure (17) is formed comprising floating gates (16) and control gates (15). The layer structure is provided with windows (18) through which UV radiation can reach the edges of the floating gates. The memory is further provided with means for generating an electric voltage between the substrate (10) and the control gates (16) during programming the memory by means of UV radiation. Thus, the memory can be programmed without being externally contacted during programming.

Abstract: A device contains a memory that stores a WOM codeword that encodes successive generations of data values. When the codeword must be updated to represent a new data value, the device determines which updates of the dataword can be realized by feasible single bit updates to the WOM codeword. If no feasible single bit update is possible, feasible two-bit updates are considered. Under control of the new data values a connection circuit routes feasibility signals for various updates, that signal the single-bit feasibility of the updates. Routing brings together pairs of feasibility signals for updates that together produce a WOM codeword that encodes the new data value. A pair is selected in which both feasibility signals indicate feasibility and the codeword is updated according to the updates involved in the pair. Preferably, the routing is realized with a connection circuit that comprises a number of layers of subcircuits, each routing the feasibility signals dependent on a respective bit of the new dataword.

Abstract: Two substantially identical currents (I1,a, I1,b) are subtracted from each other, while being generated by elements (10, 11) in such a way that noise in the current value of said two currents (I1,a, I1,b) is determined by shot noise. The differential current, determined only by shot noise, is supplied to a capacitor (13). A second current (I2) is used to charge a second capacitor (22, 29). It is periodically determined whether the value of a voltage across the first capacitor (13) is within or outside a range bounded by the (negative and positive values of the) voltage of the second capacitor (22, 29) which has been charged over the same period of time. The currents (I1,b, Ib) are set in dependence on the result of the comparison. The signal to set the currents (I1,b, Ib) also serves as control signal for an element (43) connected as a constant current source.

Abstract: A semiconductor device comprising a non-volatile memory cell, for storing at least one bit, in a semiconductor substrate (1) having, in the substrate, a source region (6), a drain region (7) and a channel region (10) between the source (6) and drain (7) regions, and having, on top of the substrate, a floating gate (9) separated from the channel region (10) by a floating gate insulating layer, a select gate (11) adjacent to the floating gate and separated from the channel region by a select gate insulating layer (8), and a control gate (5) separated from the floating gate (9) by a control gate insulating layer, the floating gate being a non-conducting charge trapping dielectric layer (9).

Abstract: One-time UV-programmable read-only memory (1) comprising a number of memory cells in the form of MOS transistors (T) which are arranged in a matrix of rows and columns, each transistor comprising a source and a drain zone (12) and a channel zone (13) formed in a surface zone (11) of a semiconductor substrate (10). Said semiconductor zones adjoin a surface (14) of the semiconductor substrate on which surface a layer structure (17) is formed comprising floating gates (16) and control gates (15). The layer structure is provided with windows (18) through which UV radiation can reach the edges of the floating gates. The memory is further provided with means for generating an electric voltage between the substrate (10) and the control gates (16) during programming the memory by means of UV radiation. Thus, the memory can be programmed without being externally contacted during programming.