Abstract: An electronic device may include a source memory device partitioned into N elementary source memories for storing a sequence of input data sets, and a processor clocked by a clock signal and having N outputs for producing, per cycle of the clock signal, N output data sets respectively associated with the N input data sets stored in the N elementary source memories at respective source addresses. The electronic device may also include N single port target memories, N interleaving tables including, for each relative source address, the number of a target memory and the respective target address thereof, N cells connected in a ring structure. Further, each cell may also be connected between an output of the processor, an interleaving table, and a target memory.

Abstract: In a particular embodiment using a distributed architecture, the electronic device comprises a source memory means partitioned in N elementary source memories for storing a sequence of input data, processing means clocked by a clock signal and having N outputs for producing per cycle of the clock signal N data respectively associated to N input data respectively stored in the N elementary source memories at relative source addresses, N single port target memories, N interleaving tables containing for each relative source address the number of one target memory and the corresponding relative target address therein, N cells connected in a ring structure, each cell being further connected between one output of the processing means, one interleaving table, and the port of one target memory, each cell being adapted to receive data from said output of the processing means and from its two neighbouring cells or to write at least some of these received data sequentially in the associated target memory, in accordance

Abstract: An electronic device may include a source memory device partitioned into N elementary source memories for storing a sequence of input data sets, and a processor clocked by a clock signal and having N outputs for producing, per cycle of the clock signal, N output data sets respectively associated with the N input data sets stored in the N elementary source memories at respective source addresses. The electronic device may also include N single port target memories, N interleaving tables including, for each relative source address, the number of a target memory and the respective target address thereof, N cells connected in a ring structure. Further, each cell may also be connected between an output of the processor, an interleaving table, and a target memory.

Abstract: In a particular embodiment using a distributed architecture, the electronic device comprises a source memory means partitioned in N elementary source memories for storing a sequence of input data, processing means clocked by a clock signal and having N outputs for producing per cycle of the clock signal N data respectively associated to N input data respectively stored in the N elementary source memories at relative source addresses, N single port target memories, N interleaving tables containing for each relative source address the number of one target memory and the corresponding relative target address therein, N cells connected in a ring structure, each cell being further connected between one output of the processing means, one interleaving table, and the port of one target memory, each cell being adapted to receive data from said output of the processing means and from its two neighbouring cells or to write at least some of these received data sequentially in the associated target memory, in accordance