Abstract: A transport stream parser is described. In particular, the transport stream parser is incorporated in a host system such as a set top box. The transport stream parser operates on a data stream having a plurality of packets that have MPEG data. Specifically, sometime after the transport stream is received by the host system, the transport stream is directed to the transport stream parser. The transport stream parser selects TS (transport stream) packets from the transport stream by searching for a first plurality of codes in a first portion of each TS packet. Moreover, the transport stream parser scans a data payload of the selected TS packets for a second plurality of codes to determine a plurality of parsing result codes. In addition, the transport stream parser adds a parsing result word having the parsing result codes to each TS packet.

Abstract: A method and system for interfacing video and graphics data. Specifically, the present invention discloses a method and system for displaying video and graphics data of different formats and image frequencies onto the same display line. A master device that is continually streaming data of a first media type to a display at a certain image rate requests data from a source device one line at a time. The incoming line of data is sent to a FIFO buffer. A mixer associated with the master device then aligns the incoming data to the same format and image rate used for displaying the first media type. The incoming data is then displayed simultaneously on the same line with the data of the first media type. As viewed as an image, windows of video and/or graphics data are shown on a display.

Abstract: A bidirectional parallel signal interface for providing a parallel data interface between a computer and an external peripheral device includes an interface circuit with command registers for communicating commands and data, a first-in, first-out (FIFO) memory for communicating data between the computer and the peripheral device, and host and slave state machines for receiving commands from the command registers and in accordance therewith controlling communication of data between the FIFO and peripheral device and communicating control signals to and from the peripheral device. The communication of data between the FIFO and peripheral device is effected in accordance with data communication rates which are controlled by the host and slave state machines in accordance with the commands from the command registers.

Abstract: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times.

Abstract: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead. The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communication station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times.

Abstract: An asynchronous communications element which incorporates user-selectable FIFOs both as transmitter and receiver buffers to reduce CPU interrupt overhead.The asynchronous communications element includes a receiver shift register which receives serial data transfers from a communications station, a receiver FIFO which receives parallel data transfers from the receiver shift register for transfer to the CPU, a transmitter FIFO which receives parallel data transfers from the CPU, and a transmitter shift register which receives parallel data transfers from the transmitter FIFO for serial transfer to the communications station. A transmitter time delay eliminates multiple interrupts for a transmitter FIFO "empty" condition that has already been indicated to the CPU. Programmable interrupt levels on the receiver FIFO, together with a receiver FIFO that continues to fill beyond the programmed interrupt level, allow adjustments for variable CPU latency times.