Abstract: Systems, methods, and other embodiments are described that are associated with selective shorting of clock branches. In one embodiment, an apparatus includes a selective shorting device connected between a first clock branch that conducts a slow clock signal having a first frequency and a second clock branch that conducts a fast clock signal having a second frequency that is an integer multiple of the first frequency. The selective shorting device is configured to electrically connect and disconnect the first clock branch and the second clock branch. The selective shorting control mechanism is configured to control the selective shorting device to electrically connect the clock branches during a controlling portion of the slow clock signal.

Abstract: According to some embodiments, an apparatus having corresponding methods includes a storage module configured to store data and instructions; a first processor pipeline configured to process the data and instructions when the first processor pipeline is selected; a second processor pipeline configured to process the data and instructions when the second processor pipeline is selected; and a selection module configured to select either the first processor pipeline or the second processor pipeline.

Abstract: Systems, methods, and other embodiments associated with selective shorting are described. According to one embodiment, an apparatus includes a selective shorting device connected between clock branches. The selective shorting device is configured to selectively electrically connect the clock branches to one another and to selectively electrically disconnect the clock branches from one another. The apparatus also includes a selective shorting control mechanism that controls the selective shorting device to electrically connect the clock branches during a controlling portion of a clock signal. The selective shorting control mechanism is configured to electrically disconnect the clock branches in the absence of the controlling portion.

Abstract: Systems, methods, and other embodiments associated with selective shorting are described. According to one embodiment, an apparatus includes a selective shorting device connected between clock branches. The selective shorting device is configured to selectively electrically connect the clock branches to one another and to selectively electrically disconnect the clock branches from one another. The apparatus also includes a selective shorting control mechanism that controls the selective shorting device to electrically connect the clock branches during a controlling portion of a clock signal. The selective shorting control mechanism is configured to electrically disconnect the clock branches in the absence of the controlling portion.

Abstract: A device can include 1) a sustained or constantly powered low leakage latch to and from which a volatile state is uploaded and downloaded, respectively, based on an active-to-low signal, and 2) an intermittently powered or de-powerable memory element, coupled to the low leakage latch, from which and to which the volatile state is uploaded and downloaded, respectively, based on the active-to-low signal and a de-powerable voltage across the de-powerable memory element is powered and un-powered, respectively.

Abstract: The present invention relates to a process for the preparation of micronised sterile steroids, comprising sterilisation of the steroids in crystalline form by means of irradiation with gamma or beta rays, and subsequent sterile micronisation.

Abstract: A memory driver architecture and associated methods are generally described.

Abstract: A memory driver architecture and associated methods are generally described.

Abstract: A level translator block receives a control signal and a data signal and provides an interface between circuitry operating in a first voltage domain and circuitry operating in a second voltage domain. Thick-oxide transistors are appropriately used in the level translator block to reduce gate leakage currents when translating signals.

Abstract: An integrated circuit having a state retentive memory structure to store state values. A high performance section uses thin gate-oxide transistors and the state retentive memory structure uses thick gate-oxide transistors to capture and retain the state values when operating in a low power mode.

Abstract: Techniques and apparatuses for reducing power consumption in processor based systems during active and standby modes. A low power TLB is disclosed that does not precharge invalid entries or write to output circuits physical addresses that are the same as immediately preceding lookups. A circuit to acknowledge that the integrated circuits of the processor have entered low power standby mode that is low leakage and consumes little power is disclosed. Minimum delay buffers that have very low leakage because of series placement of a long delay enable transistor with the transistors of the inverters that make up the buffers is also disclosed.

Abstract: An integrated circuit having a state retentive memory structure to store state values. A high performance section uses thin gate-oxide transistors and the state retentive memory structure uses thick gate-oxide transistors to capture and retain the state values when operating in a low power mode.

Abstract: A level translator block receives a control signal and a data signal and provides an interface between circuitry operating in a first voltage domain and circuitry operating in a second voltage domain. Thick-oxide transistors are appropriately used in the level translator block to reduce gate leakage currents when translating signals.

Abstract: An integrated circuit having CMOS transistors processed with different gate-oxide thicknesses. The transistors having the thinner gate-oxide may be used to generate data values that may be stored by the transistors having the thicker gate-oxides. The thicker gate-oxides may reduce gate leakage currents during a system standby mode.

Abstract: An integrated circuit having CMOS transistors processed with different gate-oxide thicknesses. The transistors having the thinner gate-oxide may be used to generate data values that may be stored by the transistors having the thicker gate-oxides. The thicker gate-oxides may reduce gate leakage currents during a system standby mode.

Abstract: A multiprocessor data processing system includes a private data bus and a private program bus coupled to each of the processors. Coupled between the private data buses is a plurality of memory banks, each of which can be dynamically switched between the processors to move blocks of data without physically transferring the data from one bank to another. Likewise, a plurality of memory banks is coupled between the program buses. These memory banks are loaded with pages of program instructions from external memory over a shared bus. Any one of the pages can be coupled to either of the processors on its respective private program bus. When the pages are coupled to the shared bus, they appear as a contiguous address space. When a page is coupled to one of the private program buses, the addressing mode is changed so that the page is mapped to a common address space.