Abstract: The interface circuit has a single input terminal for receiving an analog or digital control signal indicative of the required speed of rotation of the motor. The type of input signal is recognised by means of comparator circuits. The input signal is processed differently according to its nature in order, in any case, to output an analog signal acceptable by the regulation and control circuit which pilots the motor.

Abstract: The circuit includes a differential voltage/current converter (V/I) for connection to the sensor (S), a differential transresistance amplifier (TDA) whose inputs are connected to the outputs of the converter (V/I), and a double-ended/single-ended converter (D/S) connected to the outputs of the amplifier (TDA). The circuit is conveniently formed as an integrated circuit by CMOS P-well technology.

Abstract: A control circuit for a half-wave brushless motor. The control circuit includes n circuit branches, each with an electronic power switch connected in series with the respective winding or phase of the motor across the terminals of a voltage source in parallel to the other n-1 circuit branches, a pilot circuit for providing enabling signals to render the power switches selectively conductive, current recirculation elements for dissipating transient current that flows in each phase of the motor whenever the associated power switch is turned off, and a voltage limiter for limiting, to a predetermined threshold voltage, the voltage surge due to the transient current.

Abstract: The circuit comprises synchronisation devices operable to provide, for a motor having n phases, n square wave control signals phase displaced from one another by 360/n electrical degrees, with a frequency proportional to the speed of the rotor of the motor, and linear feedback pilot circuit devices operable to provide at their output, cyclically to each of the power transistors, which pilot the phases, a respective pilot signal variable as a function of a reference signal and the voltage on the corresponding phases of the motor.

Abstract: The interface circuit described comprises a plurality of control stages, each of which can detect and indicate a short-circuit in the corresponding load or the associated power transistor.In particular, the interface circuit is arranged to disable a transistor permanently when short-circuits occur repeatedly in the load in order to prevent damage to the transistor.

Abstract: The circuit comprises an amplitude limiter made up with the use of two CMOS transistors and a circuit connected to the output of the amplitude limiter for filtering the signal and changing its level. The filtering and level-changing circuit is arranged, in particular, to achieve band-pass filtering in order to prevent aliasing effects which might arise during the sampling of the signal by subsequent switched-capacitance processing circuits, and to attenuate low-frequency components of the signal.

Abstract: The device includes two channels for detecting and processing the signal provided by an accelerometric sensor, operating in two frequency bands in which peaks indicative of pinking (knocking) may occur. In each combustion phase, a third channel, also connected to the sensor, provides a signal representative of the noise component of the signal from the sensor, in a frequency band in which the peaks do not occur. The signals provided by the first and second channels are integrated and then compared with a reference signal generated in dependence on the noise component detected cylinder by cylinder. The device thus enables pinking to be detected cylinder by cylinder.

Abstract: A switched-capacitor circuit is described, which performs the functions of a full-wave rectifier and of an integrator and has a single operational amplifier and a comparator. The circuit is insensitive to the stray capacitances and offsets of the comparator and the operational amplifier. In particular, the input signal is sampled during only one phase of the clock which pilots the operation of the switched-capacitance network.

Abstract: An automatic system for adjusting the output impedance of fast CMOS drivers, wherein the output impedance of a plurality of slaved drives is adjusted by a circuit for measuring and correcting mismatch between the output impedance of one of the drivers, taken as reference and dedicated for this purpose, and the impedance at the input of a reference transmission line, equal to the lines connected to the other drivers. The measuring of the output impedance of the reference drive is indirectly effected by inserting at the reference drive input a clock signal and by periodically measuring the output on the reference transmission line in correspondence with the positive half-period center.

Abstract: The source is apt to generate a fully-differential reference voltage at the output terminals, whereto precisely-balanced loads are applied. The voltage reference is obtained from a bandgap voltage source fed with currents proportional to the temperature, in order to minimize thermal voltage variations. Suitable circuits for starting the normal source operation after switching on are also provided.

Abstract: Voltage reference is generated by a current generator which, through a current-mirror amplifier, biases an enhancement MOS transistor as well as a depletion one, so that the desired voltage is equal to the difference between their threshold voltages.