Abstract: The invention is directed towards a processing apparatus for a portable communication device. The apparatus includes: a central processing unit, first and second digital signal processing units, a first dual port memory unit adapted to store data shared between the central processing unit and the first digital signal processing unit, and a second dual port memory unit adapted to store data shared between the central processing unit and the second digital signal processing unit. The first dual port memory unit is adapted to store data shared between the first and second digital signal processing units without using the central processing unit.

Abstract: The invention is directed towards a processing apparatus for a portable communication device. The apparatus includes: a central processing unit, first and second digital signal processing units, a first dual port memory unit adapted to store data shared between the central processing unit and the first digital signal processing unit, and a second dual port memory unit adapted to store data shared between the central processing unit and the second digital signal processing unit. The first dual port memory unit is adapted to store data shared between the first and second digital signal processing units without using the central processing unit.

Abstract: A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external memory (EM), via a memory bus (MB) having an N-bit width, and comprising i) an embedded processor (EP) adapted to run the program, ii) an internal memory (IM) for storing at least a bootstrap code of this program, iii) an external memory interface (EMI) connected to the memory bus (MB), and iv) a processor bus (PB) connecting the internal memory (IM) and the external memory interface (EMI) to the embedded processor (EP). The external memory (EM) also stores, at a chosen address, an N-bit data word (C) having a value representative of its size (equal to N/8 bits) and of the Endian form of the stored program data.

Abstract: A control device (D) is a part of an integrated circuit (IC) comprising at least two cores (C1, C2) coupled, via buses (BC1, BC2), to a memory (M) arranged to store data to be transferred between these cores (C1, C2). This control device (D) comprises at least one flag register (FR1, FR2) coupled to the cores (C1, C2) via the buses (BC1, BC2) and arranged to store, at Ni addresses, Ni flag values associated to data stored into the memory (M) by one of the cores and ready to be transferred towards the other core, each flag value stored at a first address being able to be set or reset by one of the cores (C1, C2) by means of a command designating the first address, thus authorizing another flag value stored at a second address to be simultaneously set or reset by the other core (C2, C1) by means of a command designating the second address.

Abstract: The baseband processor (18) comprises: a storage unit (72) storing: a descriptor table comprising for each descriptor: a pointer field designed to point to a definition of an operation, an absolute operation time field indicating at which time from the beginning of a frame processing the corresponding operation should be carried out, an operation definition table comprising for each operation a definition of the operation, each definition having a sequence of events, each event of the definition table being associated with a relative event time field indicating at which time from the beginning of the operation the corresponding event should be executed, and a calculator (70) to automatically compute a list of events from the description and operation tables.

Abstract: A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external memory (EM), via a memory bus (MB) having an N-bit width, and comprising i) an embedded processor (EP) adapted to run the program, ii) an internal memory (IM) for storing at least a bootstrap code of this program, iii) an external memory interface (EMI) connected to the memory bus (MB), and iv) a processor bus (PB) connecting the internal memory (IM) and the external memory interface (EMI) to the embedded processor (EP). The external memory (EM) also stores, at a chosen address, an N-bit data word (C) having a value representative of its size (equal to N/8 bits) and of the Endian form of the stored program data.

Abstract: A control device (D) is a part of an integrated circuit (IC) comprising at least two cores (C1,C2) coupled, via buses (BC1, BC2), to a memory (M) arranged to store data to be transferred between these cores (C1, C2). This control device (D) comprises at least one flag register (FR1, FR2) coupled to the cores (C1,C2) via the buses (BC1, BC2) and arranged to store, at Ni addresses, Ni flag values associated to data stored into the memory (M) by one of the cores and ready to be transferred towards the other core, each flag value stored at a first address being able to be set or reset by one of the cores (C1, C2) by means of a command designating the first address, thus authorizing another flag value stored at a second address to be simultaneously set or reset by the other core (C2,C1) by means of a command designating the second address.

Abstract: The baseband processor (18) comprises: a storage unit (72) storing: a descriptor table comprising for each descriptor: a pointer field designed to point to a definition of an operation, an absolute operation time field indicating at which time from the beginning of a frame processing the corresponding operation should be carried out, an operation definition table comprising for each operation a definition of the operation, each definition having a sequence of events, each event of the definition table being associated with a relative event time field indicating at which time from the beginning of the operation the corresponding event should be executed, and a calculator (70) to automatically compute a list of events from the description and operation tables.