Abstract: A linear MOSFET device includes a shield plate positioned between a drain and an overlying gate. A voltage bias is applied to the shield plate to maintain linear operation of the device for RF power amplification. An AC ground is preferably connected to the shield plate. The voltage bias can be varied for matching of parallel connected devices, for responding to peak input signals, and for temperature compensation.

Abstract: In a method of fabricating a self-aligned bipolar junction transistor with silicide extrinsic base contacts and selective epitaxial grown intrinsic base region, the sinker and buried N+ layer regions are formed in a semiconductor substrate with trench oxide isolation. Thin oxide is then formed on the structure. Next, metal silicide is deposited on the thin oxide and p-dopant implanted into the silicide. LTO is then deposited on the doped silicide followed by deposition of nitride. Next, the nitride, LTO and silicide layers are etched, stopping on the thin oxide layer. The thin oxide is then etched to expose the silicon. The etch undercuts the thin oxide under the nitride. A thin p+ epitaxial base is then selectively grown on the silicon and the metal silicide only. The base can be silicon or a silicon germanium layer to form a heterojunction transistor. Next, thin LTO is deposited followed by deposition of nitride. An RIE of the nitride is then performed to form nitride spacers, stopping on the thin LTO.