Abstract: A method for obtaining an integrated device that includes: forming a metal barrier layer above a substrate; forming an anodizable metal layer on the metal barrier layer; anodizing a first region and a second region of the anodizable metal layer to obtain respectively a first porous region and a second porous region both having a plurality of substantially straight pores that extend from a top surface of the porous region towards the metal barrier layer; forming an etching mask above at least the first porous region having an opening above the second porous region; and etching bottom ends of pores of the second porous region through the opening of the etching mask to obtain pores that form a device region, and pores in the first porous region that form a dicing line, the integrated device being delimited at least by the dicing line.

Abstract: The present invention describes an ultra High-Density Capacitor design, integrated in a semiconductor substrate, preferably a Si substrate, by using both wafer sides. The capacitors are pillar-shaped and comprise electrodes (930,950) separated by a dielectric layer (940). Via connections (920) are provided in trenches that go through the whole thickness of the wafer.

Abstract: The present invention describes an ultra High-Density Capacitor design, integrated in a semiconductor substrate, preferably a Si substrate, by using both wafer sides. The capacitors are pillar-shaped and comprise electrodes (930,950) separated by a dielectric layer (940). Via connections (920) are provided in trenches that go through the whole thickness of the wafer.