Abstract: A FIFO (first-in-first-out) buffer register in which memory data words flow in parallel from an input register through a plurality of registers towards an output register under the automatic control of a one-shot (monostable multivibrator) data transfer system. A one-shot device and a status flip-flop are associated with each individual register in the plurality of registers to asynchronously transfer a data word register-by-register from the input register to the register nearest the output register that is not occupied by a previously inputted data word. The automatic data word transfer system is initiated by either reading a word into the input register or reading a word out of the output register. Logic controls for handling the reading-in and reading-out functions operate asynchronously and independently.