Patents by Inventor Frank E. Abboud

Frank E. Abboud has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7851109
    Abstract: Low stress reticle pellicle assemblies. In accordance with certain embodiments of the present invention, a pellicle frame of reduced stiffness is employed to reduce the stress a pellicle frame induces in a reticle plate. In other embodiments, a pellicle frame of reduced adhesive surface is employed to reduce the stress a pellicle frame induces in a reticle plate. In accordance with still other embodiments, a stress compensating frame is employed to reduce the cumulative stresses in an assembly comprising the reticle plate, pellicle and stress compensating frame.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: December 14, 2010
    Assignee: Intel Corporation
    Inventors: Kishore K. Chakravorty, Frank E. Abboud, Henry Yun
  • Patent number: 7847566
    Abstract: A method of testing electronic devices on substrates is described. The method includes placing a configurable prober over a first substrate, testing the first substrate, re-configuring the configurable prober, placing the configurable prober over a second substrate, and testing the second substrate.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: December 7, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Matthias Brunner, Shinichi Kurita, Ralf Schmid, Fayez (Frank) E. Abboud, Benjamin Johnston, Paul Bocian, Emanuel Beer
  • Publication number: 20090246644
    Abstract: Low stress reticle pellicle assemblies. In accordance with certain embodiments of the present invention, a pellicle frame of reduced stiffness is employed to reduce the stress a pellicle frame induces in a reticle plate. In other embodiments, a pellicle frame of reduced adhesive surface is employed to reduce the stress a pellicle frame induces in a reticle plate. In accordance with still other embodiments, a stress compensating frame is employed to reduce the cumulative stresses in an assembly comprising the reticle plate, pellicle and stress compensating frame.
    Type: Application
    Filed: March 31, 2008
    Publication date: October 1, 2009
    Inventors: Kishore K. Chakravorty, Frank E. Abboud, Henry Yun
  • Patent number: 7319335
    Abstract: An improved prober for an electronic devices test system is provided. The prober is “configurable,” meaning that it can be adapted for different device layouts and substrate sizes. The prober generally includes a frame, at least one prober bar having a first end and a second end, a frame connection mechanism that allows for ready relocation of the prober bar to the frame at selected points along the frame, and a plurality of electrical contact pins along the prober bar for placing selected electronic devices in electrical communication with a system controller during testing. In one embodiment, the prober is be used to test devices such as thin film transistors on a glass substrate. Typically, the glass substrate is square, and the frame is also square. In this way, “x” and “y” axes are defined by the frame.
    Type: Grant
    Filed: July 12, 2004
    Date of Patent: January 15, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Matthias Brunner, Shinichi Kurita, Ralf Schmid, Fayez (Frank) E. Abboud, Benjamin Johnston, Paul Bocian, Emanuel Beer
  • Patent number: 5393987
    Abstract: A raster scan lithography system is modified so that the duration of illumination (dose modulation) for particular pixels is varied to lie between the full on and full off normally used. For instance, three levels of pixel intensity are provided, 100%, 70% and 30% (in addition to off which is 0%). The 30% and 70% pixels are used along the edge of a feature so as to locate the edge when written in between the lines of the cartesian raster scan grid. Thus the edges of the feature are moved off the grid, without the need for multiple passes. This pixel dose modulation uses three preset delay lines determining dwell times for each pixel on a pixel-by-pixel basis, as defined by a two (or more) bit deep memory file associated with the pattern to be written. Additionally, the pixel center locations are directly moved off the grid by deflecting the beam as it scans certain pixels located along feature edges. The amount of deflection is controllably variable to achieve various edge locations.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: February 28, 1995
    Assignee: ETEC Systems, Inc.
    Inventors: Frank E. Abboud, Andrew J. Muray, C. Neil Berglund