Patents by Inventor Frank Findeis

Frank Findeis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7344896
    Abstract: Methods of forming ferromagnetic liners on the top surface and sidewalls of conductive lines of magnetic memory devices. The ferromagnetic liners increase the flux concentration of current run through the conductive lines, reducing the amount of write current needed to switch magnetic memory cells. In one embodiment, an in-bound pole is formed at the bottom edge of conductive lines, further concentrating the flux.
    Type: Grant
    Filed: July 26, 2004
    Date of Patent: March 18, 2008
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Rainer Leuschner, Wolfgang Raberg, Stephen L. Brown, Frank Findeis, Sivanandha K. Kanakasabapathy, Michael Vieth
  • Patent number: 7001783
    Abstract: Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices that avoid shorting magnetic memory cells to upper levels of conductive lines during etching processes. One method involves using a hard mask having two material layers to pattern the lower magnetic material layers of an MTJ. The first material of the hard mask is thin and comprises an etch-resistant material. The second material of the hard mask deposited over the first material is thicker and is less etch-resistant than the first material. At least a portion of the second material is sacrificially removed during the etch process of the lower magnetic material layers. A conformal or non-conformal material may be used as the second material of the hard mask. The hard mask used to pattern lower magnetic materials of an MTJ may comprise a single layer of non-conformal material.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: February 21, 2006
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Gregory Costrini, Frank Findeis, Gill Yong Lee, Chanro Park
  • Publication number: 20060019487
    Abstract: Methods of forming ferromagnetic liners on the top surface and sidewalls of conductive lines of magnetic memory devices. The ferromagnetic liners increase the flux concentration of current run through the conductive lines, reducing the amount of write current needed to switch magnetic memory cells. In one embodiment, an in-bound pole is formed at the bottom edge of conductive lines, further concentrating the flux.
    Type: Application
    Filed: July 26, 2004
    Publication date: January 26, 2006
    Inventors: Rainer Leuschner, Wolfgang Raberg, Stephen Brown, Frank Findeis, Sivanandha Kanakasabapathy, Michael Vieth
  • Patent number: 6985384
    Abstract: A magneto resistive memory device is fabricated by etching a blanket metal stack comprised of a buffer layer, pinned magnetic layer, a tunnel barrier layer and a free magnetic layer. The problem of junction shorting from resputtered metal during the etching process is eliminated by formation of a protective spacer covering the side of the freelayer and tunnel barrier interface. The spacer is formed following the first etch through the free layer which stops on the barrier layer. After spacer formation a second etch is made to isolate the device. The patterning of the device tunnel junction is made using a disposable mandrel method that enables a self-aligned contact to be made following the completion of the device patterning process.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: January 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: Gregory Costrini, John Hummel, Kia-Seng Low, Igor Kasko, Frank Findeis, Wolfgang Raberg
  • Publication number: 20050277207
    Abstract: Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices that avoid shorting magnetic memory cells to upper levels of conductive lines during etching processes. One method involves using a hard mask having two material layers to pattern the lower magnetic material layers of an MTJ. The first material of the hard mask is thin and comprises an etch-resistant material. The second material of the hard mask deposited over the first material is thicker and is less etch-resistant than the first material. At least a portion of the second material is sacrificially removed during the etch process of the lower magnetic material layers. A conformal or non-conformal material may be used as the second material of the hard mask. The hard mask used to pattern lower magnetic materials of an MTJ may comprise a single layer of non-conformal material.
    Type: Application
    Filed: June 15, 2004
    Publication date: December 15, 2005
    Inventors: Gregory Costrini, Frank Findeis, Gill Lee, Chanro Park
  • Publication number: 20040229430
    Abstract: A magnetic random access memory device having a magnetic tunnel junction is provided, as well as methods of fabricating the same. The magnetic tunnel junction includes a first magnetic layer, a second magnetic layer, a tunnel barrier layer, and dielectric material portions. The first magnetic layer is formed over the second magnetic layer. The tunnel barrier layer is located between the first and second magnetic layers. The dielectric material portions are formed on sidewalls of the first magnetic layer and over the second magnetic layer. The dielectric material portions may be formed directly atop the second magnetic layer. In another embodiment, the dielectric material portion may be formed directly atop the tunnel barrier layer. Preferably, the dielectric material portions prevent shorts from developing across the tunnel barrier layer during the etching of the second magnetic layer.
    Type: Application
    Filed: May 14, 2003
    Publication date: November 18, 2004
    Inventors: Frank Findeis, Ihar Kasko, Wolfgang Raberg
  • Patent number: 6812141
    Abstract: Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be used. These aggresive processing steps offer the possibility of fabricating new device architectures. In addition, by encapsulating the areas of metallization, metal ion migration and electromigration can be prevented. Further, the encapsulated areas of metallization can serve as a self-aligning etch mask. Thus, vias etched between adjacent areas of metallization allow the area of the substrate allocated to the via to be significantly reduced without increasing the possibility of electrical shorts to the adjacent areas of metallization.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: November 2, 2004
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Michael C. Gaidis, Joachim Nuetzel, Walter Glashauser, Eugene O'Sullivan, Gregory Costrini, Stephen L. Brown, Frank Findeis, Chanro Park