Abstract: A quantum computing system having a central controller with improved latency executes a first instruction at a processing unit of the central controller. The central controller interconnects a plurality of control entities for configuring and measuring a plurality of qubits. A set of selected channels carry measurement results for a first quantum computation by the plurality of qubits. When the first instruction is a multi-channel-receive instruction, the system stalls the processing unit from executing any further instructions until each channel of the set of two or more selected channels has provided an input from a remote peer. Different channels in the set of selected channels are examined simultaneously. The system resumes execution at the processing unit of a second instruction after the stalling.

Abstract: A quantum computing system that supports efficient multitasking receives messages from a classical computing system to a pool of qubits. Each received message is associated with a partition identifier. The system configures a first set of qubits in the pool of qubits to perform a first computing task based on received messages that are associated with a first partition identifier and a second set of qubits in the pool of qubits to perform a second computing task based on received messages that are associated with a second partition identifier. The system acquires a first set of measurements from the first set of qubits and a second set of measurements from the second set of qubits. The system relays the first and second sets of measurements to the classical computing system.

Abstract: A computer program product for data compression is provided. The computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and executable by a processing circuit to cause the processing circuit to execute software compression for first requests for data compression that have respective sizes below a predefined threshold, forward second requests for data compression having respective sizes above the predefined threshold to a hardware accelerator and maintain a persistence of a compression dictionary used for executing the second requests across executions of the first and second requests.

Abstract: A computer program product for data compression is provided. The computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and executable by a processing circuit to cause the processing circuit to execute software compression for first requests for data compression that have respective sizes below a predefined threshold, forward second requests for data compression having respective sizes above the predefined threshold to a hardware accelerator and maintain a persistence of a compression dictionary used for executing the second requests across executions of the first and second requests.

Abstract: A computer program product for data compression is provided. The computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and executable by a processing circuit to cause the processing circuit to execute software compression for first requests for data compression that have respective sizes below a predefined threshold, forward second requests for data compression having respective sizes above the predefined threshold to a hardware accelerator and maintain a persistence of a compression dictionary used for executing the second requests across executions of the first and second requests.

Abstract: A computer program product for data compression is provided. The computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and executable by a processing circuit to cause the processing circuit to execute software compression for first requests for data compression that have respective sizes below a predefined threshold, forward second requests for data compression having respective sizes above the predefined threshold to a hardware accelerator and maintain a persistence of a compression dictionary used for executing the second requests across executions of the first and second requests.

Abstract: A method, system, and computer program product to dynamically determine the applicability of a hardware accelerator to a request for a function, the request including a set of blocks of input data, are described. Aspects include storing a decision of whether to use the hardware accelerator or a software module to execute the function based on a previously processed request and determining whether the request matches the previously processed request. Aspects also include processing the set of blocks of input data using the hardware accelerator or the software module according to the decision based on the request matching the previously processed request.

Abstract: A method, system, and computer program product to dynamically determine the applicability of a hardware accelerator to a request for a function, the request including a set of blocks of input data, are described. Aspects include storing a decision of whether to use the hardware accelerator or a software module to execute the function based on a previously processed request and determining whether the request matches the previously processed request. Aspects also include processing the set of blocks of input data using the hardware accelerator or the software module according to the decision based on the request matching the previously processed request.

Abstract: Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software, the work queue entry comprising a first ATS field that describes a structure of the work queue entry. Another aspect includes, based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator. Another aspect includes, based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, rejecting the work queue entry by the hardware accelerator.

Abstract: Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software, the work queue entry comprising a first ATS field that describes a structure of the work queue entry. Another aspect includes, based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator. Another aspect includes, based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, rejecting the work queue entry by the hardware accelerator.

Abstract: Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

Abstract: Embodiments relate to providing a data stream interface for offloading the inflation/deflation processing of data to a stateless compression accelerator. An aspect includes transmitting a request to inflate or deflate a data stream to a compression accelerator. The request may include references to an input buffer for storing input data from the data stream, an output buffer for storing processed input data, and a state data control block for storing a stream state. The stream state is provided to the compression accelerator to continue processing the data stream responsive to the request being a subsequent request. The compression accelerator is instructed to store a current stream state in the state data control block responsive to the request being a non-final request. Accordingly, the current stream state is received from the compression accelerator responsive to the request being a non-final request. The processed input data is received from the compression accelerator.

Abstract: Embodiments relate to providing a data stream interface for offloading the inflation/deflation processing of data to a stateless compression accelerator. An aspect includes transmitting a request to inflate or deflate a data stream to a compression accelerator. The request may include references to an input buffer for storing input data from the data stream, an output buffer for storing processed input data, and a state data control block for storing a stream state. The stream state is provided to the compression accelerator to continue processing the data stream responsive to the request being a subsequent request. The compression accelerator is instructed to store a current stream state in the state data control block responsive to the request being a non-final request. Accordingly, the current stream state is received from the compression accelerator responsive to the request being a non-final request. The processed input data is received from the compression accelerator.

Abstract: Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

Abstract: Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

Abstract: Embodiments relate to providing a data stream interface for offloading the inflation/deflation processing of data to a stateless compression accelerator. An aspect includes transmitting a request to inflate or deflate a data stream to a compression accelerator. The request may include references to an input buffer for storing input data from the data stream, an output buffer for storing processed input data, and a state data control block for storing a stream state. The stream state is provided to the compression accelerator to continue processing the data stream responsive to the request being a subsequent request. The compression accelerator is instructed to store a current stream state in the state data control block responsive to the request being a non-final request. Accordingly, the current stream state is received from the compression accelerator responsive to the request being a non-final request. The processed input data is received from the compression accelerator.

Abstract: Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated.

Abstract: Mechanisms, in a multi-chip data processing system, for performing a boot process for booting each of a plurality of processor chips of the multi-chip data processing system are provided. With these mechanisms, a multi-chip agnostic isolated boot phase operation is performed, in parallel, to perform an initial boot of each of the plurality of processor chips as if each of the processor chips were an only processor chip in the multi-chip data processing system. A multi-chip aware isolated boot phase operation of each of the processor chips is performed in parallel, where each of the processor chips has its own separately configured address space. In addition, a unified configuration phase operation is performed to select a master processor chip from the plurality of processor chips and configure other processor chips in the plurality of processor chips to operate as slave processor chips that are controlled by the master processor chip.

Abstract: Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software, the work queue entry comprising a first ATS field that describes a structure of the work queue entry. Another aspect includes, based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator. Another aspect includes, based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, rejecting the work queue entry by the hardware accelerator.

Abstract: Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software, the work queue entry comprising a first ATS field that describes a structure of the work queue entry. Another aspect includes, based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator. Another aspect includes, based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, rejecting the work queue entry by the hardware accelerator.