Abstract: A semiconductor nonvolatile memory cell (30) comprising a split-gate FET device having a charge-storage transistor (38) in series with a select transistor (39). A multilayered charge-storage gate dielectric (35) extends over at least a portion of the source (32) and a first portion (341) of the channel of the FET. A select gate dielectric (36), contiguous to the charge-storage gate dielectric, extends over at least a portion of the drain (33) and a second portion (342) of the channel. A monolithic gate conductor (37) overlies both the charge-storage gate dielectric and the select gate dielectric. In an embodiment, the charge-storage gate dielectric is an ONO stack that incorporates a thin-film nitride charge-storage layer (352). The select transistor operates to inhibit over-erasure of the NVM cell. The thin-film nitride charge-storage layer extends laterally over a substantial portion of the channel so as to enhance data retention by the cell.

Abstract: A technique for reducing the read gate voltage in a memory array including memory cells having a transistor for storing charge indicative of the value stored in the cell. In one example, a voltage greater than the substrate voltage is applied to the sources of the transistors of the memory cells of the array to increase the threshold voltage of a transistor due the body effect. The read gate voltage is greater than the source voltage which is greater than the substrate voltage. A non read voltage of less than the source voltage is applied to the gates of the transistors of the unselected rows to reduce leakage current. With this embodiment, the threshold voltages of transistors having an erased state can be less than 0V. With some embodiments, the read disturb caused by a gate voltage can be reduced due to the reduction in the gate voltage. In other examples, a negative voltage is applied to the gates of unselected rows to prevent leakage current.