Abstract: A semiconductor device is produced by providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, and introducing dopant atoms of a first doping type and dopant atoms of a second doping type into the epitaxial layer.

Abstract: In an embodiment, a semiconductor device includes a silicon carbide layer comprising a lateral diode, and a Group III nitride based semiconductor device arranged on the silicon carbide layer.

Abstract: A semiconductor device is produced by providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, and introducing dopant atoms of a first doping type and dopant atoms of a second doping type into the epitaxial layer.

Abstract: A transistor includes a source, a drain spaced apart from the source, and a heterostructure body having a two-dimensional charge carrier gas channel for connecting the source and the drain. The transistor further includes a semiconductor field plate disposed between the source and the drain. The semiconductor field plate is configured to at least partly counterbalance charges in the drain when the transistor is in an off state in which the channel is interrupted and a blocking voltage is applied to the drain. The counterbalance charge provided by the semiconductor field plate is evenly distributed over a plane or volume of the semiconductor field plate. Various semiconductor field plate configurations and corresponding manufacturing methods are described herein.

Abstract: A semiconductor device includes a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device and the second semiconductor device are integrated to form a half-bridge. The third semiconductor device is a normally-off semiconductor device that is arranged in series with the half-bridge.

Abstract: An embodiment electronic device comprises a semiconductor chip including a first main face, a second main face and side faces each connecting the first main face to the second main face. A metal layer is disposed above the second main face and the side faces, the metal layer including a porous structure.

Abstract: An electronic device includes a first transistor device with first contact elements, a second transistor device with second contact elements, and an electrical connection member with a first main face and a second main face opposite to the first main face. The first transistor device is disposed on the first main face of the electrical connection member and the second transistor device is disposed on the second main face of the electrical connection member. One of the first contact elements is electrically connected with one of the second contact elements by a part of the electrical connection member.

Abstract: In an embodiment, a semiconductor device includes a silicon carbide layer comprising a lateral diode, and a Group III nitride based semiconductor device arranged on the silicon carbide layer.

Abstract: A transistor includes a source, a drain spaced apart from the source, and a heterostructure body having a two-dimensional charge carrier gas channel for connecting the source and the drain. The transistor further includes a semiconductor field plate disposed between the source and the drain. The semiconductor field plate is configured to at least partly counterbalance charges in the drain when the transistor is in an off state in which the channel is interrupted and a blocking voltage is applied to the drain. The counterbalance charge provided by the semiconductor field plate is evenly distributed over a plane or volume of the semiconductor field plate. Various semiconductor field plate configurations and corresponding manufacturing methods are described herein.

Abstract: An embodiment electronic device comprises a semiconductor chip including a first main face, a second main face and side faces each connecting the first main face to the second main face. A metal layer is disposed above the second main face and the side faces, the metal layer including a porous structure.

Abstract: An electronic device includes a first transistor device with first contact elements, a second transistor device with second contact elements, and an electrical connection member with a first main face and a second main face opposite to the first main face. The first transistor device is disposed on the first main face of the electrical connection member and the second transistor device is disposed on the second main face of the electrical connection member. One of the first contact elements is electrically connected with one of the second contact elements by a part of the electrical connection member.

Abstract: A semiconductor device includes a device region. The device region includes at least one device region section including dopant atoms of a first doping type and with a first doping concentration of at least 1E16 cm?3 and dopant atoms of a second doping type and with a second doping concentration of at least 1E16 cm?3.

Abstract: A die structure includes a die and a metallization layer disposed over the front side of the die. The metallization layer includes copper. At least a part of the metallization layer has a rough surface profile. The part with the rough surface profile includes a wire bonding region, to which a wire bonding structure is to be bonded.

Abstract: An embodiment electronic device comprises a semiconductor chip including a first main face, a second main face and side faces each connecting the first main face to the second main face. A metal layer is disposed above the second main face and the side faces, the metal layer including a porous structure.

Abstract: A die structure includes a die and a metallization layer disposed over the front side of the die. The metallization layer includes copper. At least a part of the metallization layer has a rough surface profile. The part with the rough surface profile includes a wire bonding region, to which a wire bonding structure is to be bonded.

Abstract: The present invention relates to an integrated transformer configuration having a first coil formed from an electrically conductive material having a spiral course with an essentially rectangular cross section. The transformer has a second coil with a spiral course. The first and the second coils are arranged such that they are electrically insulated from one another. The ratio between the height and the width of the rectangular cross section of the first coil is greater than 1.

Abstract: A power switching device has a power switching transistor connected in series in a load circuit with an inductive load portion and a commutation circuit. The commutation circuit is connected in parallel with the gate-drain or base-collector path of the power transistor and has a first Zener diode, which determines the commutation clamping voltage for switching on the power switching transistor during commutation, and an oppositely biased normal diode that is connected in series with the first Zener diode. The commutation circuit further has control elements in order to reduce, during a short time, the commutation clamping voltage at the beginning of each commutation cycle or after an adjustable delay from the beginning of each commutation cycle.

Abstract: The present invention relates to an integrated transformer configuration having a first coil formed from an electrically conductive material having a spiral course with an essentially rectangular cross section. The transformer has a second coil with a spiral course. The first and the second coils are arranged such that they are electrically insulated from one another. The ratio between the height and the width of the rectangular cross section of the first coil is greater than 1.

Abstract: A power switching device has a power switching transistor connected in series in a load circuit with an inductive load portion and a commutation circuit. The commutation circuit is connected in parallel with the gate-drain or base-collector path of the power transistor and has a first Zener diode, which determines the commutation clamping voltage for switching on the power switching transistor during commutation, and an oppositely biased normal diode that is connected in series with the first Zener diode. The commutation circuit further has control elements in order to reduce, during a short time, the commutation clamping voltage at the beginning of each commutation cycle or after an adjustable delay from the beginning of each commutation cycle.