Patents by Inventor Frank Kelsey
Frank Kelsey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10825512Abstract: A memory includes a row decoder that receives an address of a row to be read and an operand. The memory includes a memory array of bitcells that can be configured to store N-bit weight values in which N is an integer greater than one. The row decoder is configured to, for a multiplication mode read operation at the selected word line, selectively activate the selected word line based on a bit value of the received operand to selectively read an N-bit weight value based on a bit value of the operand. Such an operation may in some embodiments, perform a multiplication operation of the bit value of the operand and the N-bit weight value.Type: GrantFiled: August 27, 2019Date of Patent: November 3, 2020Assignee: NXP USA, INC.Inventors: Frank Kelsey Baker, Jr., Thomas Jew, Ronald J. Syzdek
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Publication number: 20180260014Abstract: A memory system has a memory array divided into a plurality of sub-arrays in which each sub-array has a mutually exclusive power domain, task scheduler circuitry coupled to the memory array, and sub-array power control circuitry coupled to the task scheduler circuitry. A method includes selecting, by the task scheduler circuitry, a task for execution, providing a control signal to the sub-array power control circuitry indicative of a set of sub-arrays to power based on the selected task, and setting a power state of each sub-array, by the sub-array control circuitry, in response to the control signal.Type: ApplicationFiled: March 7, 2017Publication date: September 13, 2018Inventors: Patrice M. PARRIS, Weize CHEN, Md M. HOQUE, Frank Kelsey BAKER, JR., Victor WANG, Joachim Josef Maria KRUECKEN
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Publication number: 20080241323Abstract: Disclosed herein is a system for sanitizing objects, particularly food products such as fruits and vegetables. The system includes two or more tanks for generation and storage of chlorine dioxide. The system provides for the simultaneous use and generation of chlorine dioxide so that the system avoids undesired down-time.Type: ApplicationFiled: April 2, 2007Publication date: October 2, 2008Inventors: D. Frank Kelsey, Johnnie M. Harden
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Patent number: 7135370Abstract: A non-volatile memory (NVM) cell, which uses a storage dielectric as the storage element, has a top dielectric between a gate and the storage dielectric and a bottom dielectric between a semiconductor substrate and the storage dielectric. The top dielectric includes a relatively thick and high k dielectric layer and an interfacial layer. The interfacial layer is very thin and has a higher k than silicon oxide. The bottom dielectric layer is preferably silicon oxide because of its interfacial and tunneling properties. The cell thus has benefits resulting from a well-passivated, high k top dielectric in combination with a bottom dielectric of silicon oxide.Type: GrantFiled: July 1, 2004Date of Patent: November 14, 2006Assignee: Freescale Semiconductor, Inc.Inventor: Frank Kelsey Baker
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Patent number: 6812517Abstract: A non-volatile memory (NVM) cell, which uses a storage dielectric as the storage element, has a top dielectric between a gate and the storage dielectric and a bottom dielectric between a semiconductor substrate and the storage dielectric. The top dielectric includes a relatively thick and high k dielectric layer and an interfacial layer. The interfacial layer is very thin and has a higher k than silicon oxide. The bottom dielectric layer is preferably silicon oxide because of its interfacial and tunneling properties. The cell thus has benefits resulting from a well-passivated, high k top dielectric in combination with a bottom dielectric of silicon oxide.Type: GrantFiled: August 29, 2002Date of Patent: November 2, 2004Assignee: Freescale Semiconductor, Inc.Inventor: Frank Kelsey Baker
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Publication number: 20040041192Abstract: A non-volatile memory (NVM) cell, which uses a storage dielectric as the storage element, has a top dielectric between a gate and the storage dielectric and a bottom dielectric between a semiconductor substrate and the storage dielectric. The top dielectric includes a relatively thick and high k dielectric layer and an interfacial layer. The interfacial layer is very thin and has a higher k than silicon oxide. The bottom dielectric layer is preferably silicon oxide because of its interfacial and tunneling properties. The cell thus has benefits resulting from a well-passivated, high k top dielectric in combination with a bottom dielectric of silicon oxide.Type: ApplicationFiled: August 29, 2002Publication date: March 4, 2004Inventor: Frank Kelsey Baker
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Patent number: 6444545Abstract: A semiconductor device structure for storing charge has a silicon nitride layer, in which a plurality of nanoclusters are sandwiched between oxide layers. The nanoclusters and the silicon nitride make up a storage region, which is particularly useful in non-volatile memories. The nanoclusters provide a repository for holes or electrons that jump from trap to trap in the silicon nitride when the silicon nitride is heated. This results in much of the charge, which would normally leak off from the silicon nitride at high temperatures, remaining in the storage region due to trapping in the nanoclusters. The silicon nitride layer with nanoclusters therein is formed by depositing a silicon nitride layer, then nanoclusters, and then another silicon nitride layer or by depositing a silicon-rich silicon nitride layer and subsequent heating to cause it to transform to a regular silicon nitride layer with silicon nanoclusters therein.Type: GrantFiled: December 19, 2000Date of Patent: September 3, 2002Assignee: Motorola, Inc.Inventors: Michael A. Sadd, Sucharita Madhukar, Frank Kelsey Baker
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Publication number: 20020076850Abstract: A semiconductor device structure for storing charge has a silicon nitride layer, in which a plurality of nanoclusters are sandwiched between oxide layers. The nanoclusters and the silicon nitride make up a storage region, which is particularly useful in non-volatile memories. The nanoclusters provide a repository for holes or electrons that jump from trap to trap in the silicon nitride when the silicon nitride is heated. This results in much of the charge, which would normally leak off from the silicon nitride at high temperatures, remaining in the storage region due to trapping in the nanoclusters. The silicon nitride layer with nanoclusters therein is formed by depositing a silicon nitride layer, then nanoclusters, and then another silicon nitride layer or by depositing a silicon-rich silicon nitride layer and subsequent heating to cause it to transform to a regular silicon nitride layer with silicon nanoclusters therein.Type: ApplicationFiled: December 19, 2000Publication date: June 20, 2002Inventors: Michael A. Sadd, Sucharita Madhukar, Frank Kelsey Baker
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Patent number: 6133093Abstract: In one embodiment, the reliability of an integrated circuit having a floating gate device (50), a high breakdown voltage transistor (52), and a low breakdown voltage transistor (54), which are electrically isolated from each other by a trench isolation region (12), is improved by using an oxidation resistant layer (24). The oxidation resistant layer (24) protects portions of the trench isolation region (12) when the gate dielectric layer (30) for the high breakdown voltage transistor (52) is formed, and when the gate dielectric layer (36) for the low breakdown voltage transistor (54) is formed. The oxidation resistant layer (24) minimizes etching of the field isolation region (12) so that thinning or recessing of the field isolation region (12) is minimized.Type: GrantFiled: January 30, 1998Date of Patent: October 17, 2000Assignee: Motorola, Inc.Inventors: Erwin J. Prinz, Gregory M. Yeric, Kevin Yun-kang Wu, Wei-Ming Chen, Frank Kelsey Baker
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Patent number: 6101130Abstract: An electrically erasable programmable read only memory (EEPROM) array (30) that includes rows and columns of memory cells. Word lines (WL0 and WL1) are substantially parallel to each other and extend in a first direction. Drain bit lines (BL0-B13) and source lines (SL0 and SL1) are substantially parallel to each other and extend in a second direction that is perpendicular to the first direction. The source line (SL0) and source regions of at least two memory cells (31 and 36) within the EEPROM array are electrically connected by a first source local interconnect (LI1). The first source local interconnect (LI1) has a length that extends substantially in the first direction and electrically connects some, but not all, of the memory cells lying within the EEPROM array (30).Type: GrantFiled: June 29, 1999Date of Patent: August 8, 2000Assignee: Motorola Inc.Inventors: Frank Kelsey Baker, Juan Buxo, Danny Pak-Chum Shum, Thomas Jew
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Patent number: 5888570Abstract: A method of operating a drenching apparatus for drenching fruit and vegetables with an aqueous chemical solution having a pit for holding a large volume of the solution, a drench pump for drawing the solution from the pit and discharging it into manifolds equipped with nozzles for drenching the fruit, recovery apparatus for returning excess solution to the pit which is a holding tank for holding a volume of the solution; a heater, including a heater pump, connected to the holding tank and arranged to maintain the temperature of the solution therein; a re-circulation pump connected to draw solution from the pit and direct it to a heater with a conduit connecting said holding tank to said pit. The volume of the holding tank being sufficient to assure that portions of the solution are maintained at said temperature for a time to eradicate pathogens.Type: GrantFiled: June 4, 1997Date of Patent: March 30, 1999Assignee: FMC CorporationInventors: Clint P. Arrington, D. Frank Kelsey
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Patent number: 5850783Abstract: An improved drench apparatus for drenching fruit and vegetables with an aqueous chemical solution having a pit for holding a large volume of said solution, drench pump for drawing solution from the pit and discharging it into manifolds equipped with nozzles for drenching the fruit, a recovery system for returning excess solution to the pit; comprising a holding tank for holding a volume of said solution; a heater, including a heater pump, connected to said holding tank and arranged to maintain the temperature of the solution therein; a re-circulation pump connected to draw solution from said pit and direct it to said heater with a conduit connecting said holding tank to said pit. The volume of said holding tank being sufficient to assure portions of the solution are maintained at said temperature for a time to eradicate pathogens.Type: GrantFiled: May 31, 1996Date of Patent: December 22, 1998Assignee: FMC CorporationInventors: Clint P. Arrington, D. Frank Kelsey
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Patent number: 5741736Abstract: A semiconductor device (83)including a transistor (85) with a nonuniformly doped channel region can be formed with a relatively simple process without having to use high dose implants or additional heat cycles. In one embodiment, a polysilicon layer (14) and silicon nitride layer (16) are patterned at the minimum resolution limit. The polysilicon layer is then isotropically etched to form a winged gate structure (32). A selective channel implant step is performed where ions are implanted through at least one of the nitride wings of the winged gate structure (32) but are not implanted through the polysilicon layer (14). Another polysilicon layer (64)is conformally deposited and etched such that the polysilicon (74) does not extend beyond the edges of the nitride wings.Type: GrantFiled: May 13, 1996Date of Patent: April 21, 1998Assignee: Motorola Inc.Inventors: Marius K. Orlowski, Frank Kelsey Baker, Jr.
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Patent number: 5739564Abstract: A static-random-access memory cell comprising floating node capacitors is disclosed. In one embodiment, the storage nodes acts as the first plates for the floating node capacitors, and a conductive member acts as the second plates for the floating node capacitors. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cell. In another embodiment, a conductive member acts as the second plates of a plurality of memory cells. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cells. Processes for forming the memory cells is also disclosed.Type: GrantFiled: June 1, 1995Date of Patent: April 14, 1998Assignee: Motorola, Inc.Inventors: Yasunobu Kosa, Howard C. Kirsch, Thomas F. McNelly, Frank Kelsey Baker
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Patent number: 4803819Abstract: This relates to reinforced hollow utility poles, and attachments therefore, formed by pultrusion of dielectric insulating material, such as glass fiber reinforced resin, and the method of fabricating the same.Type: GrantFiled: November 3, 1986Date of Patent: February 14, 1989Inventor: Frank Kelsey