Abstract: The present invention relates to a system for asynchronous transmission and reception of data between control units. The system includes a first control unit which is operatively connected to a first asynchronous transmitter-receiver circuit, a second control unit operatively connected to a second asynchronous transmitter-receiver circuit and a single media connected between the first and second control units, which facilitates serial communication of data therebetween. Each asynchronous transmitter receiver circuit includes a transmitter portion having circuit for separately processing odd data bits and even data bits at a rate between 1 MHz and 40 MHz, and a receiver portion for processing received data signals and extracting the odd and even data bits therefrom.

Abstract: A circuit for retiming asynchronous data. A sampling clock is derived in which the system clock frequencies are no higher than that of the data frequency. The leading edge of the signal from a received data-to-clock position circuit and a bias distortion circuit are combined and decoded to determine the center of the received data to select the proper sampling clock for the received data.

Abstract: A transceiver for use in a local area network presents a high impedance to the cable when the transceiver is in its off state, that is, when it is not in the transmit mode. During the off state, the transformer that couples the transceiver to the cable is isolated from the transmitter section by reverse-biased diodes, which are forward biased when the transceiver is in the transmit or low-impedance mode.