Abstract: An embodiment of the invention provides a memory on a semiconductor device that has a plurality of memory areas where each memory area has a plurality of consecutive bits. Further, the semiconductor device includes a tag memory having a plurality of trace tags, each trace tag including at least one bit. Each memory area of the memory is mapped to a trace tag that indicates whether the respective memory area is selected for tracing or not. Each memory area and the assigned trace tag are read out and address of the memory area is forwarded to a trace module when an assigned trace tag indicates that the memory area is selected for tracing. When the assigned trace tag indicates that the memory area is not selected for tracing, data and address is discarded.

Abstract: An embodiment of the invention provides a memory on a semiconductor device that has a plurality of memory areas where each memory area has a plurality of consecutive bits. Further, the semiconductor device includes a tag memory having a plurality of trace tags, each trace tag including at least one bit. Each memory area of the memory is mapped to a trace tag that indicates whether the respective memory area is selected for tracing or not. Each memory area and the assigned trace tag are read out and address of the memory area is forwarded to a trace module when an assigned trace tag indicates that the memory area is selected for tracing. When the assigned trace tag indicates that the memory area is not selected for tracing, data and address is discarded.

Abstract: The present invention relates to a microcontroller including a central processing unit, at least one memory, a bus coupling the storage location to the central processing unit, and a data modification module for modifying data in the at least one memory. The data modification module includes a first interface being coupled to the bus for transferring data to the at least one memory over the bus, and a second interface being adapted to be coupled to an external device for receiving the data, wherein the data modification module is adapted to operate as a bus master and to transfer data received from the external device over the bus to the at least one memory.

Abstract: The present invention relates to a microcontroller including a central processing unit, a storage location, a bus coupling the storage location to the central processing unit, and a data modification module for modifying data in the storage location. The data modification module includes a first interface being coupled to the bus for transferring data to the storage location over the bus, and a second interface being adapted to be coupled to an external device for receiving the data, wherein the data modification module is adapted to operate as a bus master and to transfer data received from the external device over the bus to the storage location.

Abstract: The present invention relates to a microcontroller comprising a central processing unit, a memory, a bus coupling the memory to the central processing unit, and a memory trace module for tracing at least one of a data of a write access to memory or data of a read access from the memory. The memory trace module comprises a first interface being coupled to the bus for capturing at least one of the data or corresponding address information on the bus, and a second interface being adapted to be coupled to an external device, wherein the memory trace module is adapted to transfer data from the first to the second interface and from the second interface to the external device.

Abstract: An interrupt timer module comprises a prescale counter (PSC) incremented by a real-time interrupt clock signal (RTICLK), a prescale compare value register (CVR) storing a configurable value (PCV), a comparator comparing the current count of the prescale counter (PSC) with the stored configurable value (PCV), a free running counter (FRC) incremented by a match from the comparator, and a plurality of interrupt generation units (IGU0, IGU1, IGU2) Each interrupt generation unit (IGU0, IGU1, IGU2) comprises a compare value register (CVR0, CVR1, CVR2) storing a compare value and a comparator comparing the compare value from the respective compare value register with the current count of the free running counter providing one or both of an interrupt signal (INT0, INT1, INT2) and a direct memory request signal (DMAREQ0, DMAREQ1, DMAREQ2) upon a match.

Abstract: A timer module for generating interrupts to a system including a microcontroller that provides a real-time interrupt using a dedicated real-time interrupt clock signal (RTICLK), comprises a prescale counter (PSC) incremented by the real-time interrupt clock signal (RTICLK),a prescale compare value register (CVR) for storing a configurable value (PCV), a comparator for comparing the current count of the prescale counter (PSC) with the stored configurable value (PCV), a free running counter (FRC) incremented by a match from the comparator, and a plurality of interrupt generation units (IGU0, IGU1, IGU2) each having an input receiving the current count of the free running counter (FRC).