Abstract: Multiple voltage regulators for use with a single load. The present invention allows power to be supplied to an electrical load using multiple voltage regulators based on the operating environment of the load. In one embodiment, a primary voltage regulator that is built of relatively low capacity and relatively high efficiency components is used to supply power from a limited power source. A secondary voltage regulator built of higher capacity and possibly lower efficiency components is used when power is from a less limited source. In one embodiment, a tertiary voltage regulator is used that is built of possibly higher capacity and lower efficiency components to provide even more power. It is important to note that use of voltage regulators as described herein does not require that higher capacity voltage regulators be less efficient than lower capacity voltage regulators.

Abstract: A method and apparatus for facilitating power state control and awareness of an autonomous subsystem in a computer based system without involvement of the main operating system.

Abstract: A method and apparatus for booting the operating environment of an autonomous subsystem in a computer based system without involvement of the main operating system are described.

Abstract: A method and apparatus for facilitating direct access to a serial Advanced Technology Attachment (ATA) device by an autonomous subsystem in the absence of the main operating system (OS).

Abstract: A method and apparatus for facilitating direct access to a parallel Advanced Technology Attachment (ATA) device by an autonomous subsystem in the absence of the main operating system (OS).

Abstract: A method and apparatus for access to resources not mapped to an autonomous subsystem in a computer based system without involvement of the main operating system are described.

Abstract: A system for controlling operation of a computer includes a first processor in the computer and a second processor in a docking station. The first and second processors shift a context for controlling the computer between the computer and the docking station based on detecting an event relating to docking. If the context is shifted to the computer in response to undocking, the first processor controls the computer and the second processor halts operation. If the context is shifted to the docking station in response to docking, the second processor controls the computer and the first processor halts operation.

Abstract: The present invention is a memory bus connector for accommodating a memory module that is parallel to a motherboard. The memory bus connector of the present invention has a plurality of individual contacts that act as data signal contacts and/or ground members that connect to the lower portion the parallel memory module. The memory bus connector of the present invention also has a sheet grounding member that connects to the upper portion of the memory module.

Abstract: A method and apparatus for facilitating direct access to a parallel Advanced Technology Attachment (ATA) device by an autonomous subsystem in the absence of the main operating system (OS).

Abstract: A method and apparatus for facilitating direct access to a serial Advanced Technology Attachment (ATA) device by an autonomous subsystem in the absence of the main operating system (OS).

Abstract: The present invention is a memory bus connector for accommodating a memory module that is parallel to a motherboard. The memory bus connector of the present invention has a plurality of individual contacts that act as data signal contacts and/or ground members that connect to the lower portion the parallel memory module. The memory bus connector of the present invention also has a sheet grounding member that connects to the upper portion of the memory module.

Abstract: The present invention is a memory bus connector for accommodating a memory module that is parallel to a motherboard. The memory bus connector of the present invention has a plurality of individual contacts that act as data signal contacts and/or ground members that connect to the lower portion the parallel memory module. The memory bus connector of the present invention also has a sheet grounding member that connects to the upper portion of the memory module.

Abstract: A method and apparatus for converting a signal from a first voltage level to a second voltage level before providing the signal to a processor. A circuit board includes an interface for coupling the circuit board to a peripheral subsystem via a socket. The circuit board also includes a processor that receives signals of a first voltage level, a first signal line, and a second signal line. The first signal line is coupled to the interface and provides a reference signal to the peripheral subsystem that indicates the first voltage level. The second signal line is also coupled to the interface and provides a subsystem signal back from the peripheral subsystem after the signal has been converted to the first voltage level.

Abstract: A method and apparatus for upgrading a computer system from one processor generation to another processor generation. The processor and its corresponding primary bridge are included together on the same circuit board. The circuit board has an interface which can be inserted into a socket of a system. The interface socket includes the memory bus and peripheral component bus from the bridge.

Abstract: A method and apparatus for adjusting the clock frequency and voltage supplied to an integrated circuit. First, a signal is sent to the clock, and in response, the clock lowers the clock frequency supplied to the integrated circuit. The clock sends a signal to the voltage regulator whereupon the voltage regulator reduces the voltage supplied to the integrated circuit.