Abstract: A plurality of doped areas (12, 13, 14) are formed on a surface of a semiconductor wafer. A titanium nitride layer (17) is used for covering the plurality of doped areas (12, 13, 14) and for providing electrical connection between the doped areas (12, 13, 14). The titanium nitride layer (17) substantially prevents dopants from diffusing into the titanium nitride ( 17 ) and subsequently counterdoping the doped areas (12, 13, 14) during subsequent high temperature processing operations.

Abstract: Briefly stated, the present invention provides a vertical current flow semiconductor device (17). The vertical current flow semiconductor device (17) includes a semiconductor substrate (12) having an intermediate conductor layer (16) on a surface of the substrate (12). An active layer (11) that is used for forming active elements (20, 21, 22, 23) of the vertical current flow semiconductor device (17) is on the intermediate conductor layer (16). The intermediate conductor layer (16) forms an ohmic contact with the active layer (11).

Abstract: A method for joining a number of first and second wafers (11,12) having one polished surface in preparation for direct wafer bonding is provided. The method involves placing a number of first (11) and the same number of second (12) wafers into slots (16) of a retainer (14) so that each of the polished surfaces of the number of first wafers (11) is forced to contact one of the polished surfaces of the number of second wafers (12).

Abstract: A dielectric and conductive isolated island is fabricated by providing an active wafer having a first and a second major surface, a doped region extending from the first surface, and a trench formed at the first surface. A conductive layer is formed on the first surface and in the trench. A planarizable layer comprised of a dielectric layer is then formed on the conductive layer. A handle wafer is bonded to the planarizable layer. The active wafer and the handle wafer are heated so that the doped region diffuses along the conductive layer to form an equalized concentration of dopant along the conductive layer which diffuses into the active wafer to form the doped region adjacent all of the conductive layer. A portion of the second surface of the active wafer is then removed so that at least a portion of the dielectric layer of the planarizable layer is exposed.

Abstract: A method of fabricating a silicon film with improved thickness control and low defect density. The method comprises implanting a silicon wafer (19) with hydrogen ions to produce a layer of n-type silicon (18) having a precisely controlled thickness. Bonding the n-type silicon layer (18) to an oxidized surface (17) of a handle wafer (21) while using a temperature of 200 degrees Celsius. Etching the silicon wafer (19) to the boundary of the n-type layer (18). Annealing the silicon to drive out the hydrogen ions, leaving a silicon film (18) with a precisely controlled thickness and of the same type as the original silicon wafer (19).

Abstract: An intermediate contact layer (16) is created within a vertical current flow semiconductor device such as an enhanced insulated gate bipolar transistor (EIGBT) (17). An active wafer (11) that is used for forming active elements of the device is wafer bonded to a conductor (16) that is on a surface of a substrate wafer (12). The wafer bonding not only forms the intermediate contact layer (16) but also diffuses a series of P (18) and N (19) regions into the active wafer (11) thereby forming ohmic contacts between the P (18) and N (19) regions and the intermediate contact layer (16). The substrate wafer (12) provides support for the active wafer (11) during subsequent wafer processing operations.

Abstract: A method of fabricating a low voltage, deep junction semiconductor device includes providing first and second wafers of opposite conductivity types, each having a dopant concentration of at least 4.0.times.10.sup.16 atoms/cc. After cleaning the wafers and removing heavy metal impurities therefrom by gettering, the wafers are bonded together. This method results in the successful fabrication of semiconductor devices having a junction depth in the range of 20 to 500 microns and a breakdown voltage of less than 20 volts.

Abstract: An apparatus and method for improved wafer bonding by scrubbing, spin drying, aligning, and pressing the polished wafers together. The first wafer (13) is mounted on a flat wafer chuck (11) and a second wafer (14) is mounted on a convex pressure gradient chuck (10). Wafers are scrubbed until a polished contamination free surface is obtained and pressed together. The convex pressure gradient chuck exerts a higher pressure at the center of the wafer than at the periphery of the wafer.

Abstract: A method and product for monocrystalline semiconductor buried layer contacts formed from recrystallized polycrystalline buried layers.

Abstract: A silicon wafer bonding technique is described utilizing low pressures and a dissolvable gas to substantially eliminate voids formed between the bonding surfaces of two wafers.